公开(公告)号：US06334198B1

公开(公告)日：2001-12-25

申请号：US09283171

申请日：1999-04-01

申请人： Swaroop Adusumilli ,  James Steele ,  David Cassetti

发明人： Swaroop Adusumilli ,  James Steele ,  David Cassetti

IPC分类号： G01R3128

CPC分类号： G01R31/318558 ,  G01R31/318563

摘要： An arrangement controls an IC designed with multiple “core” circuits, such as multiple CPUs, with each core circuit including its own TAP controller and with multiple TAP controllers enabled at a time. For applications typically requiring that control be transferred between such TAP controllers, one embodiment of the present invention configures a TLM-based design such that multiple TAP controllers can be simultaneously enabled. This alleviates the need to actually transfer the control from one TAP controller to the next. To maintain consistency with the IEEE JTAG recommendation, the TLM-based design is configured such that only one TAP is enabled upon reset. After reset, the TLM controls the multiply-enabled TAP controllers. Another specific example implementation is directed to a circuit control arrangement for such a multi-core IC having each TAP controller generate status and test signals in response to input signals directed to each of the multiple TAP controllers. A TAP link arrangement, including a TAP link module and control signals coupled to each of the multiple TAP controllers, selectively multiplexes the input signals to the multiple TAP controllers and multiplexes the status and test signals provided by the multiple TAP controllers to an output port of the IC.

摘要翻译： 一种安排控制一个设计有多个“核心”电路（如多个CPU）的IC，每个核心电路包括其自己的TAP控制器和一次启用多个TAP控制器。 对于通常要求在这种TAP控制器之间传输控制的应用，本发明的一个实施例配置基于TLM的设计，使得可以同时启用多个TAP控制器。 这减轻了将控制从一个TAP控制器实际传输到下一个的需要。 为了保持与IEEE JTAG建议的一致性，基于TLM的设计被配置为使得在复位时仅启用一个TA​​P。 复位后，TLM控制多功能TAP控制器。 另一个具体示例实现涉及用于这种多核IC的电路控制装置，其具有每个TAP控制器响应于针对多个TAP控制器中的每一个的输入信号而产生状态和测试信号。 包括TAP链路模块和耦合到多个TAP控制器中的每一个的控制信号的TAP链路布置选择性地将输入信号复用到多个TAP控制器，并将由多个TAP控制器提供的状态和测试信号复用到 IC。

公开(公告)号：US06311302B1

公开(公告)日：2001-10-30

申请号：US09283648

申请日：1999-04-01

申请人： David Cassetti ,  James Steele ,  Swaroop Adusumilli

发明人： David Cassetti ,  James Steele ,  Swaroop Adusumilli

IPC分类号： G01R3128

CPC分类号： G01R31/318536

摘要： An arrangement controls an IC designed with multiple “TLM'ed core” circuits, such as multiple CPUs, with each core circuit including its own TAP controller and with multiple TAP controllers enabled a time. For applications typically requiring that control be transferred between such TAP controllers of various core circuits, one embodiment of the present invention expands a multiple “TLM'ed core” circuit design without changing the IEEE JTAG specification and without requiring more scan chains per TAP'ed core. One particular example embodiment includes each of the design's multiple cores including multiple test-access port (TAP) controllers, and including an internal TLM having a TLM register adapted to store a decodable instruction and a supplemental storage circuit adapted to store a coded signal. Also in the design, a chip-level TLM communicates with a common IEEE JTAG interface and with each of the multiple cores via the TLM register and the supplemental storage circuit. The chip-level TLM and the multiple cores signal use the supplemental storage circuit to indicate when instructions are to be transferred from a TLM'ed core to the chip-level TLM.

摘要翻译： 一种安排控制一个设计有多个“TLM”核心“电路的IC，如多个CPU，每个核心电路包括其自己的TAP控制器，并且启用了多个TAP控制器。 对于通常需要在各种核心电路的这种TAP控制器之间传输控制的应用，本发明的一个实施例扩展了多个“TLM”核心“电路设计而不改变IEEE JTAG规范，并且不需要每个TAP的更多的扫描链 核心。 一个具体示例性实施例包括设计的多个核心中的每一个，包括多个测试访问端口（TAP）控制器，并且包括具有适于存储可解码指令的TLM寄存器的内部TLM和适于存储编码信号的补充存储电路。 同样在设计中，芯片级TLM通过TLM寄存器和补充存储电路与普通的IEEE JTAG接口和多个内核中的每一个进行通信。 芯片级TLM和多核心信号使用补充存储电路来指示何时将指令从TLM的内核传送到芯片级的TLM。

公开(公告)号：US06385749B1

公开(公告)日：2002-05-07

申请号：US09283809

申请日：1999-04-01

申请人： Swaroop Adusumilli ,  James Steele ,  David Cassetti

发明人： Swaroop Adusumilli ,  James Steele ,  David Cassetti

IPC分类号： G01R3128

CPC分类号： G01R31/318563 ,  G01R31/318555

摘要： An arrangement controls an IC designed with multiple “core” circuits, such as multiple CPUs, with each core circuit including its own TAP controller. According to one example embodiment, multiple test-access port (TAP) controllers coupled to a common interface are controlled by adapting each TAP controller to receive input signals, determine if the TAP controller is enabled, and generate status signals and test signals. An output circuit responds to the TAP controllers by outputting one of the test signals respectively provided by the multiple TAP controllers, and a link module is used to maintain one of the TAP controllers enabled at a given time. The above-embodiment is useful, for example, in connection with IC applications that require an increasing number of core circuits without increasing the circuit area of the IC and/or the number of IC pins, and can be implemented to avoid changing existing structures of TAP controllers.

摘要翻译： 一种布置控制了设计有多个“核心”电路的IC，例如多个CPU，每个核心电路包括其自己的TAP控制器。 根据一个示例性实施例，耦合到公共接口的多个测试访问端口（TAP）控制器通过使每个TAP控制器适配以接收输入信号，确定TAP控制器是否被使能并产生状态信号和测试信号来控制。 输出电路通过输出由多个TAP控制器分别提供的一个测试信号来响应于TAP控制器，并且链路模块用于在给定时间内维持其中一个TAP控制器的使能。 上述实施例例如与需要越来越多的核心电路的IC应用有关，而不增加IC的电路面积和/或IC引脚的数量，并且可以实现以避免改变现有的结构 TAP控制器。

公开(公告)号：US5793992A

公开(公告)日：1998-08-11

申请号：US664107

申请日：1996-06-13

申请人： James C. Steele ,  Barry Davis ,  Philip Wszolek ,  Brian Fall ,  Swaroop Adusumilli ,  David Cassetti ,  Rodney Pesavento ,  Nick Richardson

发明人： James C. Steele ,  Barry Davis ,  Philip Wszolek ,  Brian Fall ,  Swaroop Adusumilli ,  David Cassetti ,  Rodney Pesavento ,  Nick Richardson

IPC分类号： G06F13/16 ,  G06F13/40 ,  G06F13/00 ,  G06F13/362

CPC分类号： G06F13/1605 ,  G06F13/4027 ,  G06F13/4031

摘要： A computer system in which a host bus is relieved from the burdens of data transfers between main memory and devices connected to an input/output (I/O) bus (e.g., peripheral devices). Instead, the invention operates to place most of the burden of the data transfer on an internal bus within a bus arbitration unit so that the host bus is freed up much sooner than conventionally achieved. Further, to reduce stalling of a processor seeking access to the main memory via the host bus and the internal bus, the host bus is able to gain access to the main memory using the internal bus during times in which the internal bus is temporarily not needed by the data transfer between the main memory and the peripheral devices. As a result, the computer system has substantially better performance because the host bus is available for other processing operations instead of being tied up with data transfers with peripheral devices, and because the internal bus is occasionally freed up during the data transfer between the main memory and the peripheral devices.

摘要翻译： 一种计算机系统，其中主机总线从连接到输入/输出（I / O）总线（例如，外围设备）的主存储器和设备之间的数据传输负担中减轻。 相反，本发明操作来将数据传输的大部分负担置于总线仲裁单元内的内部总线上，使得主机总线比传统实现更早地释放。 此外，为了减少寻求通过主机总线和内部总线访问主存储器的处理器的停止，主总线能够在暂时不需要内部总线的时间期间使用内部总线来访问主存储器 通过主存储器和外围设备之间的数据传输。 因此，由于主机总线可用于其他处理操作，而不是与外围设备的数据传输相关联，因此内部总线在主存储器之间的数据传输期间偶尔被释放，因此计算机系统具有显着更好的性能 和外围设备。

公开(公告)号：US5815675A

公开(公告)日：1998-09-29

申请号：US670273

申请日：1996-06-13

申请人： James C. Steele ,  Barry Davis ,  Philip Wszolek ,  Brian Fall ,  Swaroop Adusumilli ,  David Cassetti ,  Rodney Pesavento ,  Nick Richardson

发明人： James C. Steele ,  Barry Davis ,  Philip Wszolek ,  Brian Fall ,  Swaroop Adusumilli ,  David Cassetti ,  Rodney Pesavento ,  Nick Richardson

IPC分类号： G06F12/08 ,  G06F13/16

CPC分类号： G06F13/161 ,  G06F12/0835

摘要： A computer system in which a host bus is relieved from the burdens of data transfers between main memory and devices connected to an input/output (I/O) bus. Instead, the invention operates to place most of the burden of the data transfer on an internal bus within a bus arbitration unit so that the host bus is freed up much sooner than conventionally achieved. As a result, the computer system has substantially better performance because the host bus is available for other processing operations instead of being tied up with data transfers with devices (e.g., peripheral devices) connected to the I/O bus.

摘要翻译： 一种计算机系统，其中主机总线从主存储器和连接到输入/输出（I / O）总线的设备之间的数据传输负担中减轻。 相反，本发明操作来将数据传输的大部分负担置于总线仲裁单元内的内部总线上，使得主机总线比传统实现更早地释放。 因此，由于主机总线可用于其他处理操作，而不是与连接到I / O总线的设备（例如，外围设备）进行数据传输相结合，因此计算机系统具有显着更好的性能。

公开(公告)号：US06438700B1

公开(公告)日：2002-08-20

申请号：US09313933

申请日：1999-05-18

申请人： Swaroop Adusumilli

发明人： Swaroop Adusumilli

IPC分类号： G06F132

CPC分类号： G06F9/30189 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/3287 ,  G06F9/30076 ,  G06F9/30181 ,  G06F9/3877 ,  Y02D10/128 ,  Y02D10/171

摘要： The present invention is an ARM coprocessor power reduction system and method that turns off a coprocessor clock when an ARM system is performing THUMB state instructions. For example, the ARM coprocessor power reduction system and method of the present invention tracks signals from the ARM core periphery to determine if the ARM core is attempting to facilitate ARM state or THUMB state operations. The present invention compares the THUMB bit indicator in signals associated with each stage of an ARM pipeline and determines if the instructions are THUMB state instructions. If the instructions are THUMB state instructions the ARM coprocessor power reduction system and method of the present invention turns off the coprocessor clock. Turning off the coprocessor clock prevents the coprocessor registers from switching and consuming power. If an instruction fetched into an ARM pipeline is an ARM state instruction the ARM coprocessor power reduction system and method of the present invention turns the coprocessor clock back on.

摘要翻译： 本发明是一种在ARM系统执行THUMB状态指令时关闭协处理器时钟的ARM协处理器功率降低系统和方法。 例如，本发明的ARM协处理器功率降低系统和方法跟踪来自ARM内核外围的信号，以确定ARM核心是否正在尝试促进ARM状态或THUMB状态操作。 本发明比较了与ARM流水线的每一级相关联的信号中的THUMB位指示器，并确定指令是否是THUMB状态指令。 如果指令是THUMB状态指令，则本发明的ARM协处理器功率降低系统和方法关闭协处理器时钟。 关闭协处理器时钟可防止协处理器寄存器切换和消耗电力。 如果读取到ARM管线中的指令是ARM状态指令，则本发明的ARM协处理器功率降低系统和方法重新启动协处理器时钟。

公开(公告)号：US06301631B1

公开(公告)日：2001-10-09

申请号：US09239500

申请日：1999-01-28

申请人： Peter Chambers ,  Subramanian S. Meiyappan ,  Swaroop Adusumilli

发明人： Peter Chambers ,  Subramanian S. Meiyappan ,  Swaroop Adusumilli

IPC分类号： G06F1314

CPC分类号： G06F13/16

摘要： A system and method that prevents address aliasing and eliminates the unnecessary clock cycle consumed by the use of a dual address cycle when using a single address cycle to transmit a target address in a computer system including target devices having addresses of different sizes, such as 32-bit and 64-bit target devices, with 32-bit and 64-bit addresses, respectively. In addition, a combination of single address cycles and dual address cycles may be used to prevent address aliasing while permitting access to the entire address spaces of the target devices. The computer system includes a bus, an initiator device coupled to the bus, a first target device coupled to the bus, and a second target device coupled to the bus. The first target device has a first address range containing a plurality of bits, and the second target device has a second address range containing a fewer number of bits than the first address range. The second address range includes addresses that are specified according to a first prescribed value for a most significant bit. The first address range includes addresses that are specified according to a second prescribed value for the most significant bit to exclude the second address range such that the initiator device can transmit the first address to the first target device without aliasing the second address with the first address. The initiator device selects either the first address range or the second address range for the target address by specifying either the first prescribed value or the second prescribed value in the target address.

摘要翻译： 一种防止地址混叠的系统和方法，并且消除了当使用单个地址周期在包括具有不同大小的地址的目标设备的计算机系统中传送目标地址时使用双地址周期而消耗的不必要的时钟周期，诸如32 位和64位目标器件，分别具有32位和64位地址。 此外，可以使用单个地址周期和双地址周期的组合来防止地址别名，同时允许访问目标设备的整个地址空间。 计算机系统包括总线，耦合到总线的启动器设备，耦合到总线的第一目标设备以及耦合到总线的第二目标设备。 第一目标设备具有包含多个比特的第一地址范围，并且第二目标设备具有包含比第一地址范围少的比特数的第二地址范围。 第二地址范围包括根据最高有效位的第一规定值指定的地址。 第一地址范围包括根据用于排除第二地址范围的最高有效位的第二规定值指定的地址，使得发起者设备可以将第一地址发送到第一目标设备，而不将第一地址与第一地址进行混叠 。 启动器设备通过指定目标地址中的第一规定值或第二规定值来选择目标地址的第一地址范围或第二地址范围。

公开(公告)号：US06178478B1

公开(公告)日：2001-01-23

申请号：US09210103

申请日：1998-12-11

申请人： Peter Chambers ,  Subramanian S. Meiyappan ,  Swaroop Adusumilli

发明人： Peter Chambers ,  Subramanian S. Meiyappan ,  Swaroop Adusumilli

IPC分类号： G06F1300

CPC分类号： G06F13/4004 ,  G06F13/423

摘要： A system and method for preventing address aliasing when using a single address cycle to transmit a target address in a computer system that includes target devices having addresses of different ranges. The computer system comprises a bus, an initiator device coupled to the bus, a first target device coupled to the bus, and a second target device coupled to the bus. The first target device has a first address range comprising a plurality of bits, and the second target device has a second address range comprising a fewer number of bits than the first address range. The initiator device transmits a signal indicating the size of the target address and also separately transmits in a single address cycle the target address. The second target device disables its address decode logic in response to the signal from the initiator device provided that the size of the target address is greater than the second address range. The second target device is thus prevented from responding to the target address, thereby preventing address aliasing.

摘要翻译： 一种用于在使用单个地址周期在包括具有不同范围的地址的目标设备的计算机系统中发送目标地址时防止地址混叠的系统和方法。 计算机系统包括总线，耦合到总线的启动器设备，耦合到总线的第一目标设备和耦合到总线的第二目标设备。 第一目标设备具有包括多个比特的第一地址范围，并且第二目标设备具有包括比第一地址范围少的比特数的第二地址范围。 发起者设备发送指示目标地址的大小的信号，并且在单个地址周期中分别发送目标地址。 如果目标地址的大小大于第二地址范围，则第二目标设备响应于来自发起者设备的信号而禁用其地址解码逻辑。 从而防止第二目标设备响应目标地址，从而防止地址混叠。

公开(公告)号：US5761454A

公开(公告)日：1998-06-02

申请号：US703563

申请日：1996-08-27

申请人： Swaroop Adusumilli ,  Barry M. Davis ,  Brian N. Fall ,  Nicholas J. Richardson ,  Philip Wszolek

发明人： Swaroop Adusumilli ,  Barry M. Davis ,  Brian N. Fall ,  Nicholas J. Richardson ,  Philip Wszolek

IPC分类号： G06F13/42 ,  G06F13/36

CPC分类号： G06F13/4226

摘要： A deadlock detection and resolution circuit for resolving a deadlock condition in a bridge circuit coupled to a memory, a host bus and a PCI bus of a computer system. The host bus and the PCI bus are configured to operate concurrently and asynchronously. The bridge circuit includes a host master circuit and a PCI slave circuit coupled between the host bus and the PCI bus and configured to service a PCI-MEMORY instruction from an external PCI master coupled to the PCI bus. A PCI master circuit and a host slave circuit within the bridge circuit couples between the PCI bus and the host bus and configured to service a CPU-PCI transaction from a CPU coupled to the host bus. The aforementioned deadlock condition occurs when the PCI-MEMORY transaction proceeds simultaneous with an issuance of the CPU-PCI transaction. The deadlock detection and resolution circuit includes first circuit for asserting an asynchronous handshake signal to the PCI slave of the bridge circuit. There is further included second circuit for determining whether the PCI slave is still able to complete the PCI-MEMORY transaction. Additionally, there is included third circuit for asserting an asynchronous handshake acknowledge signal to cancel the CPU-PCI transaction and removing the deadlock condition if the PCI slave is unable to complete the PCI-MEMORY transaction.

摘要翻译： 一种用于解决耦合到计算机系统的存储器，主机总线和PCI总线的桥式电路中的死锁状态的死锁检测和分辨率电路。 主机总线和PCI总线被配置为同时和异步地运行。 桥接电路包括主机主电路和耦合在主机总线和PCI总线之间的PCI从属电路，并配置为从耦合到PCI总线的外部PCI主机服务PCI-MEMORY指令。 桥接电路内的PCI主电路和主机从电路耦合在PCI总线和主机总线之间，并配置为从耦合到主机总线的CPU服务CPU-PCI事务。 当PCI-MEMORY事务随着CPU-PCI事务的发布而同时进行时，发生上述死锁条件。 死锁检测和分辨率电路包括用于向桥接电路的PCI从站断言异步握手信号的第一电路。 还包括用于确定PCI从站是否仍然能够完成PCI-MEMORY事务的第二电路。 另外，包括用于断言异步握手确认信号以消除CPU-PCI事务的第三电路，并且如果PCI从设备不能完成PCI-MEMORY事务，则消除死锁条件。

公开(公告)号：US07072996B2

公开(公告)日：2006-07-04

申请号：US10172814

申请日：2002-06-12

申请人： Swaroop Adusumilli ,  Satish N. Anand ,  Hemanshu Bhatnagar

发明人： Swaroop Adusumilli ,  Satish N. Anand ,  Hemanshu Bhatnagar

IPC分类号： G06F13/28

CPC分类号： G06F13/4031 ,  G06F13/28

摘要： A flexible input/output (I/O) interface allows a processing core to communicate high-speed data with a several different types of interfaces including a Direct Memory Access (DMA) interface and a streaming interface. The I/O interface includes a streaming interface for transferring streamed data from the streaming data bus to the core-processing engine, a DMA interface for transferring DMA data from the DMA data bus to the core-processing engine, and an arbiter for coordinating data transfer with the core-processing engine between the streaming interface and DMA interface. The arbiter may operate in a split-bus-mode wherein the arbiter performs the address phase for more than one channel prior to entering into the data phase. The flexible I/O interface may include a common address bus and data bus between the processing engine and the interfaces. Alternatively, a switching fabric may couple separate address and data buss of the interfaces with the processing engine.

摘要翻译： 灵活的输入/输出（I / O）接口允许处理核心将高速数据与几种不同类型的接口进行通信，包括直接存储器访问（DMA）接口和流式接口。 I / O接口包括用于将流数据从流数据总线传送到核心处理引擎的流接口，用于将DMA数据从DMA数据总线传送到核心处理引擎的DMA接口，以及用于协调数据的仲裁器 在流接口和DMA接口之间与核心处理引擎进行传输。 仲裁器可以以分流总线模式操作，其中仲裁器在进入数据阶段之前执行多于一个通道的地址相位。 灵活的I / O接口可以包括处理引擎和接口之间的公共地址总线和数据总线。 或者，交换结构可以将接口的单独的地址和数据总线与处理引擎相耦合。