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8 条记录 (耗时 0.033 秒)

    Multi-phase delay locked loop with equally-spaced phases over a wide frequency range and method thereof
    5.
    发明授权
    Multi-phase delay locked loop with equally-spaced phases over a wide frequency range and method thereof 有权
    在宽频率范围内具有等间隔相位的多相延迟锁相环及其方法

    公开(公告)号：US07675333B2

    公开(公告)日：2010-03-09

    申请号：US11760782

    申请日：2007-06-10

    申请人： Prasenjit Bhowmik ,  Sundararajan Krishnan ,  Sriram Ganesan

    发明人： Prasenjit Bhowmik ,  Sundararajan Krishnan ,  Sriram Ganesan

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0812

    摘要： A Delay Locked Loop (DLL) and method for generating multiple equally spaced phases over a wide frequency range is disclosed. The DLL includes a delay line, and a control module. The delay line receives a reference clock signal and outputs a final delay clock signal in response to the reference clock signal. The delay line includes a plurality of delay cells connected in series. The plurality of delay cells generate a plurality of delay clock signals having equally spaced phases. The control module generates a phase control signal based on counting a number of pulses of the reference clock signal that are input to the delay line before occurrence of a first corresponding pulse of the final delay clock signal.

    摘要翻译： 公开了一种用于在宽频率范围内产生多个等间隔相位的延迟锁定环（DLL）和方法。 DLL包括延迟线和控制模块。 延迟线接收参考时钟信号，并响应于参考时钟信号输出最终延迟时钟信号。 延迟线包括串联连接的多个延迟单元。 多个延迟单元产生具有相等间隔相位的多个延迟时钟信号。 控制模块基于在最终延迟时钟信号的第一对应脉冲发生之前对输入到延迟线的参考时钟信号的脉冲数进行计数来产生相位控制信号。

    Delay line with delay cells having improved gain and in built duty cycle control and method thereof
    6.
    发明授权
    Delay line with delay cells having improved gain and in built duty cycle control and method thereof 失效
    具有改善增益的延迟单元和内置占空比控制的延迟线及其方法

    公开(公告)号：US07548104B2

    公开(公告)日：2009-06-16

    申请号：US11760784

    申请日：2007-06-10

    申请人： Prasenjit Bhowmik ,  Sundararajan Krishnan ,  G. Sriram

    发明人： Prasenjit Bhowmik ,  Sundararajan Krishnan ,  G. Sriram

    IPC分类号： H03H11/26

    CPC分类号： H03K5/1565 ,  H03H11/265 ,  H03K5/133 ,  H03K2005/00045

    摘要： A delay line including a sequence of identical delay cells with improved gain and in built duty cycle distortion control and a method thereof is disclosed. Each delay cell of the sequence includes a current source, four transistors, and a load capacitor. A gate of the current source receives a voltage bias that controls a delay of the delay cell. A drain of the first transistor is connected to the drain of the current source. The first and second transistor gates receive an input clock signal. The second transistor drain is connected to the source of the current source. The third transistor gate and the load capacitor are also connected to the drain of the current source. The fourth transistor drain is connected to the third transistor drain. The fourth transistor gate is coupled to an output of a second consecutive delay cell for duty cycle distortion control.

    摘要翻译： 公开了一种包括具有改善的增益和内置的占空比失真控制的相同延迟单元序列的延迟线及其方法。 序列的每个延迟单元包括电流源，四个晶体管和负载电容器。 电流源的栅极接收控制延迟单元的延迟的电压偏置。 第一晶体管的漏极连接到电流源的漏极。 第一和第二晶体管栅极接收输入时钟信号。 第二晶体管漏极连接到电流源的源极。 第三晶体管栅极和负载电容器也连接到电流源的漏极。 第四晶体管漏极连接到第三晶体管漏极。 第四晶体管栅极耦合到用于占空比失真控制的第二连续延迟单元的输出。

    Method and system for input voltage droop compensation in video/graphics front-ends
    7.
    发明授权
    Method and system for input voltage droop compensation in video/graphics front-ends 有权
    视频/图形前端输入电压下降补偿的方法和系统

    公开(公告)号：US07570181B2

    公开(公告)日：2009-08-04

    申请号：US11760780

    申请日：2007-06-10

    申请人： Sundararajan Krishnan ,  C. Srinivasan

    发明人： Sundararajan Krishnan ,  C. Srinivasan

    IPC分类号： H03M1/06

    CPC分类号： H03M1/0607 ,  H03M1/12

    摘要： Methods and systems for input voltage droop compensation in video/graphics front-end systems. The method of an embodiment of the invention captures input voltage information supplied to an Analog-to-Digital Converter (ADC) operatively coupled to a bypass capacitor in a video/graphics front-end system; calculates a droop in the input voltage in ADC due to a charge sharing between an input sampling capacitor of the ADC and the bypass capacitor; and compensates for the value of the bypass capacitor using an output of the ADC. Embodiments of the invention provide an improved freedom in the choice of off-chip bypass capacitance in video/graphics front-end systems.

    摘要翻译： 视频/图形前端系统中输入电压下降补偿的方法和系统。 本发明的实施例的方法捕获提供给在视频/图形前端系统中可操作地耦合到旁路电容器的模数转换器（ADC）的输入电压信息; 由于ADC的输入采样电容和旁路电容之间的电荷共享，在ADC中计算输入电压的下降; 并使用ADC的输出补偿旁路电容的值。 本发明的实施例提供了在视频/图形前端系统中选择片外旁路电容的改进的自由度。

    Reducing Interference (Noise) Caused by Specific Components of a Transmitter While Receiving a Signal in a Transceiver
    8.
    发明申请
    Reducing Interference (Noise) Caused by Specific Components of a Transmitter While Receiving a Signal in a Transceiver 审中-公开
    在收发器中接收到信号时，减少发射机的特定组件引起的干扰（噪声）

    公开(公告)号：US20070127356A1

    公开(公告)日：2007-06-07

    申请号：US11164750

    申请日：2005-12-05

    申请人： Bijoy BHUKANIA ,  Sundararajan Krishnan ,  Sudheer PRASAD

    发明人： Bijoy BHUKANIA ,  Sundararajan Krishnan ,  Sudheer PRASAD

    IPC分类号： H04J3/10

    CPC分类号： H04B3/32

    摘要： A transceiver which effectively cancels interference caused by a component (e.g., driver) of a transmitter (contained in the transceiver). The input and output signals of the component are examined to estimate the magnitude of the interference, and the interference is canceled according to the estimate. Accordingly, the component need not be implemented with high accuracy/precision.

    摘要翻译： 收发器，其有效地消除由发射机的组件（例如，驱动器）引起的干扰（包含在收发器中）。 检查该组件的输入和输出信号以估计干扰的幅度，并且根据该估计消除干扰。 因此，不需要以高精度/精度实现。