利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

9 条记录 (耗时 0.017 秒)

    Semiconductor device including fin structures and manufacturing method thereof
    1.
    发明授权
    Semiconductor device including fin structures and manufacturing method thereof 有权

    公开(公告)号：US10269968B2

    公开(公告)日：2019-04-23

    申请号：US14730210

    申请日：2015-06-03

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    发明人： Yi-Jen Chen ,  Chia-Chun Liao ,  Chun-Sheng Liang ,  Shih-Hsun Chang ,  Jen-Hsiang Lu

    IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L21/02

    摘要： A method of manufacturing a semiconductor Fin FET includes forming a fin structure over a substrate. The fin structure includes an upper layer, part of which is exposed from an isolation insulating layer. A dummy gate structure is formed over part of the fin structure. The dummy gate structure includes a dummy gate electrode layer and a dummy gate dielectric layer. A source and a drain are formed. The dummy gate electrode is removed so that the upper layer covered by the dummy gate dielectric layer is exposed. The upper layer of the fin structure is removed to make a recess formed by the dummy gate dielectric layer. Part of the upper layer remains at a bottom of the recess. A channel layer is formed in the recess. The dummy gate dielectric layer is removed. A gate structure is formed over the channel layer.

    Semiconductor device with gate stacks and method of manufacturing the same
    3.
    发明授权
    Semiconductor device with gate stacks and method of manufacturing the same 有权
    具有栅极堆叠的半导体器件及其制造方法

    公开(公告)号：US09306023B2

    公开(公告)日：2016-04-05

    申请号：US14174379

    申请日：2014-02-06

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd

    发明人： Wei-Shuo Ho ,  Tsung-Yu Chiang ,  Chia-Chun Liao ,  Kuang-Hsin Chen

    IPC分类号： H01L29/76 ,  H01L29/49 ,  H01L27/088 ,  H01L21/28 ,  H01L29/66 ,  H01L29/51

    CPC分类号： H01L21/823437 ,  H01L21/28088 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

    摘要： Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a first gate stack. The first gate stack includes a gate dielectric layer, a first work function metal layer and a second work function metal layer directly on the first work function metal layer. The second work function metal layer and the first work function metal layer have the same metal element. The semiconductor device also includes a second gate stack. The second gate stack includes a gate dielectric layer, a barrier layer and a second work function metal layer. The second work function metal layer and the barrier layer do not have the same metal element. A first thickness of the second work function metal layer of the first gate stack is larger than a second thickness of the second work function metal layer of the second gate stack.

    摘要翻译： 提供了用于形成半导体器件的机构的实施例。 半导体器件包括半导体衬底和第一栅极堆叠。 第一栅极堆叠包括直接在第一功函数金属层上的栅介电层，第一功函数金属层和第二功函数金属层。 第二功函数金属层和第一功函数金属层具有相同的金属元素。 半导体器件还包括第二栅极堆叠。 第二栅极堆叠包括栅极介电层，阻挡层和第二功函数金属层。 第二功函数金属层和阻挡层不具有相同的金属元素。 第一栅极堆叠的第二功函数金属层的第一厚度大于第二栅极堆叠的第二功函数金属层的第二厚度。

    Semiconductor device and manufacturing method thereof
    5.
    发明授权
    Semiconductor device and manufacturing method thereof 有权

    公开(公告)号：US10790283B2

    公开(公告)日：2020-09-29

    申请号：US16398142

    申请日：2019-04-29

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    发明人： Chia-Chun Liao ,  Chun-Sheng Liang ,  Shu-Hui Wang ,  Shih-Hsun Chang ,  Yi-Jen Chen

    IPC分类号： H01L27/092 ,  H01L29/66 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8238

    摘要： A semiconductor device manufacturing method includes forming fins in first and second regions defined on a substrate. The fins include first fin, second fin, third fin, and fourth fin. A dielectric layer is formed over fins and a work function adjustment layer is formed over dielectric layer. A hard mask is formed covering third and fourth fins. A first conductive material layer is formed over first fin and not over second fin. A second conductive material layer is formed over first and second fins. A first metal gate electrode fill material is formed over first and second fins. The hard mask covering third and fourth fins is removed. A third conductive material layer is formed over third fin and not over fourth fin. A fourth conductive material layer is formed over third and fourth fins, and a second metal gate electrode fill material is formed over third and fourth fins.

    Semiconductor device and manufacturing method thereof
    9.
    发明授权
    Semiconductor device and manufacturing method thereof 有权

    公开(公告)号：US10276574B2

    公开(公告)日：2019-04-30

    申请号：US15211871

    申请日：2016-07-15

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    发明人： Chia-Chun Liao ,  Chun-Sheng Liang ,  Shu-Hui Wang ,  Shih-Hsun Chang ,  Yi-Jen Chen

    IPC分类号： H01L27/092 ,  H01L29/51 ,  H01L29/66 ,  H01L29/49 ,  H01L21/8238

    摘要： A semiconductor device manufacturing method includes forming fins in first and second regions defined on a substrate. The fins include first fin, second fin, third fin, and fourth fin. A dielectric layer is formed over fins and a work function adjustment layer is formed over dielectric layer. A hard mask is formed covering third and fourth fins. A first conductive material layer is formed over first fin and not over second fin. A second conductive material layer is formed over first and second fins. A first metal gate electrode fill material is formed over first and second fins. The hard mask covering third and fourth fins is removed. A third conductive material layer is formed over third fin and not over fourth fin. A fourth conductive material layer is formed over third and fourth fins, and a second metal gate electrode fill material is formed over third and fourth fins.