公开(公告)号：US09673200B2

公开(公告)日：2017-06-06

申请号：US15010798

申请日：2016-01-29

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Shih-Chi Kuo ,  Tsung-Hsien Lee ,  Ta-Ching Wei

IPC分类号： H01L21/336 ,  H01L27/11 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/027 ,  H01L21/768 ,  H01L21/762 ,  H01L21/8234

CPC分类号： H01L27/11 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32053 ,  H01L21/76205 ,  H01L21/76224 ,  H01L21/76819 ,  H01L21/76837 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/1116

摘要： A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack structure and a second gate stack structure on a substrate, and the first gate stack structure includes a first spacer adjacent to the second gate stack structure. The method also includes forming an U-shaped capping layer between the first gate stack structure and the second gate stack structure, and a lateral sidewall of the U-shaped capping layer is in direct contact with the first spacer of the first gate stack structure. A top of the lateral sidewall of the U-shaped capping layer is below a top of the first spacer of the first gate stack structure.

公开(公告)号：US09257438B2

公开(公告)日：2016-02-09

申请号：US14158220

申请日：2014-01-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd

发明人： Shih-Chi Kuo ,  Tsung-Hsien Lee ,  Ta-Ching Wei

IPC分类号： H01L21/70 ,  H01L27/11 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/027

CPC分类号： H01L27/11 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32053 ,  H01L21/76205 ,  H01L21/76224 ,  H01L21/76819 ,  H01L21/76837 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/1116

摘要： In accordance with some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a substrate, and the substrate has a cell region and a logic region. The semiconductor device structure also includes an isolation feature formed in the substrate and a first gate stack structure formed on the isolation feature and at the cell region. The semiconductor device structure further includes a second gate stack structure formed on the isolation feature and at the cell region, and the first gate stack structure is adjacent to the second gate stack structure. The isolation feature between the first gate stack structure and the second gate stack structure has a substantially planar topography.

摘要翻译： 根据一些实施例，提供半导体器件结构。 半导体器件结构包括衬底，并且衬底具有单元区域和逻辑区域。 半导体器件结构还包括形成在衬底中的隔离特征以及形成在隔离特征上和在单元区域处的第一栅极堆叠结构。 半导体器件结构还包括形成在隔离特征上和在单元区域处的第二栅极堆叠结构，并且第一栅极堆叠结构与第二栅极堆叠结构相邻。 第一栅极堆叠结构和第二栅极堆叠结构之间的隔离特征具有基本平坦的形貌。