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11 条记录 (耗时 0.019 秒)

    Non-volatile memory circuit and method
    1.
    发明授权
    Non-volatile memory circuit and method 有权

    公开(公告)号：US11450395B2

    公开(公告)日：2022-09-20

    申请号：US17237688

    申请日：2021-04-22

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Gu-Huan Li ,  Chen-Ming Hung ,  Yu-Der Chih

    IPC分类号： G11C17/00 ,  G11C17/18 ,  G11C17/16 ,  G11C8/10 ,  G11C7/10

    摘要： A memory circuit includes a first bank of non-volatile memory (NVM) devices, a first plurality of decoders, a first plurality of high-voltage (HV) drivers corresponding to the first plurality of decoders, and a first plurality of HV power switches. A first HV power switch is coupled to each HV driver of the first plurality of HV drivers, and each decoder is configured to generate an enable signal corresponding to a column of the first bank of NVM devices. Each HV driver is configured to output a HV activation signal to the corresponding column of the first bank of NVM devices responsive to a power signal of the first HV power switch and to the enable signal of the corresponding decoder.

    Integrated circuit layout, structure, system, and methods
    3.
    发明授权
    Integrated circuit layout, structure, system, and methods 有权

    公开(公告)号：US10929588B2

    公开(公告)日：2021-02-23

    申请号：US16252291

    申请日：2019-01-18

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Meng-Sheng Chang ,  Chen-Ming Hung ,  Shao-Yu Chou ,  Yao-Jen Yang

    IPC分类号： G06F17/50 ,  G06F30/392 ,  H01L27/112 ,  G11C17/16 ,  G11C17/18 ,  H01L23/528 ,  H01L23/525

    摘要： A method of generating an IC layout diagram includes intersecting an active region with first and second gate regions to define locations of first and second anti-fuse structures, overlying the first gate region with a first conductive region to define a location of an electrical connection between the first conductive region and first gate region, and overlying the second gate region with a second conductive region to define a location of an electrical connection between the second conductive region and second gate region. The first and second conductive regions are aligned along a direction perpendicular to a direction along which the first and second gate regions extend, and at least one of intersecting the active region with the first gate region, intersecting the active region with the second gate region, overlying the first gate region, or overlying the second gate region is executed by a processor of a computer.

    Anti-fuse array
    5.
    发明授权
    Anti-fuse array 有权

    公开(公告)号：US12073169B2

    公开(公告)日：2024-08-27

    申请号：US18446684

    申请日：2023-08-09

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Meng-Sheng Chang ,  Shao-Yu Chou ,  Yao-Jen Yang ,  Chen-Ming Hung

    IPC分类号： G06F7/50 ,  G06F30/392 ,  G11C17/16 ,  G11C17/18 ,  H01L23/528 ,  H10B20/20 ,  H01L23/525

    CPC分类号： G06F30/392 ,  G11C17/16 ,  G11C17/18 ,  H01L23/528 ,  H10B20/20 ,  H01L23/5252

    摘要： An anti-fuse array includes first through fourth adjacent anti-fuse bit columns, the anti-fuse bits of the first and second anti-fuse bit columns including portions of active areas of a first active area column, and the anti-fuse bits of the third and fourth anti-fuse bit columns including portions of active areas of a second active area column. Each row of a first set of conductive segment rows includes first and second conductive segments positioned between adjacent active areas of the first active area column and a third conductive segment positioned between adjacent active areas of the second active area column. Each row of a second set of conductive segments alternating with the first set of conductive segment rows includes a fourth conductive segment positioned between adjacent active areas of the first active area column and fifth and sixth conductive segments positioned between adjacent active areas of the second active area column.

    Generating stabilized output signals during fuse read operations
    10.
    发明授权
    Generating stabilized output signals during fuse read operations 有权
    在保险丝读取操作期间产生稳定的输出信号

    公开(公告)号：US09558841B2

    公开(公告)日：2017-01-31

    申请号：US13918681

    申请日：2013-06-14

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Sung-Chieh Lin ,  Kuo-Yuan Hsu ,  Wei-Li Liao ,  Chen-Ming Hung ,  Yun-Han Chen ,  Shao-Cheng Wang

    IPC分类号： G11C17/16 ,  G11C17/18

    CPC分类号： G11C17/16 ,  G11C17/18

    摘要： A circuit includes a fuse cell, a sense circuit and an output control circuit. The fuse cell includes an electrical fuse. The sense circuit is electrically coupled to the fuse cell and configured for generating a sense signal indicative of a programmed condition of the electrical fuse, at an output of the sense circuit. The output control circuit is electrically coupled to the output of the sense circuit, and the output control circuit is configured for latching the sense signal indicative of the electrical fuse having been programmed, during a read operation of the fuse cell.

    摘要翻译： 电路包括熔丝单元，感测电路和输出控制电路。 保险丝盒包括电熔丝。 感测电路电耦合到熔丝单元并且被配置为在感测电路的输出处产生指示电熔丝的编程状态的感测信号。 输出控制电路电耦合到感测电路的输出，并且输出控制电路被配置为在熔丝单元的读取操作期间锁存指示已经编程的电熔丝的感测信号。