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公开(公告)号：US20240111323A1
公开(公告)日：2024-04-04
申请号：US18169568
申请日：2023-02-15
发明人： Min-Shin Wu , Shao-Yu Chou
CPC分类号： G05F3/267 , H03F3/45179 , H03F2200/447
摘要： In some aspects of the present disclosure, a bandgap reference circuit includes a first current mirror and a first resistor coupled to the first current mirror to provide a proportional to absolute temperature (PTAT) voltage. The circuit includes a second current mirror and a bipolar junction transistor (BJT) device coupled to the second current mirror to provide a complementary to the absolute temperature (CTAT) voltage. The circuit includes an output node to provide a bandgap voltage that is a weighted sum of the PTAT voltage and the CTAT voltage. The circuit includes a second resistor coupled between the output node and a first node, wherein the first node is coupled between the first resistor and the first current mirror. The circuit includes a third resistor coupled between the output node and a second node, wherein the second node is coupled between the BJT device and the second current mirror.
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公开(公告)号：US11626368B2
公开(公告)日：2023-04-11
申请号：US17587716
申请日：2022-01-28
发明人： Meng-Sheng Chang , Shao-Yu Chou , Po-Hsiang Huang , An-Jiao Fu , Chih-Hao Chen
IPC分类号： H01L21/768 , H01L23/525 , H01L23/528 , H01L23/535 , H01L23/00
摘要： A method of making a semiconductor device includes operations directed toward electrically connecting a component to a first fuse, wherein the first fuse is on a first conductive level a first distance from the component; identifying a conductive element for omission between the first fuse and a second fuse; and electrically connecting the component to the second fuse, wherein the second fuse is on a second conductive level a second distance from the component, the second distance is greater than the first distance, and the electrically connecting the component to the second fuse comprises electrically connecting the component to the second fuse without forming the identified conductive element.
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公开(公告)号：US11569249B2
公开(公告)日：2023-01-31
申请号：US17317162
申请日：2021-05-11
发明人： Min-Shin Wu , Meng-Sheng Chang , Shao-Yu Chou , Yao-Jen Yang
IPC分类号： H01L27/00 , H01L27/112 , G11C17/18 , G11C17/16
摘要： A method of manufacturing an anti-fuse device includes forming an anti-fuse structure on a substrate, forming a first transistor at a first position away from the anti-fuse device in a first direction, and forming a second transistor at a second position away from the anti-fuse device in a second direction opposite the first direction. Forming the anti-fuse structure includes forming first and second S/D structures in an active area, the first transistor includes the first S/D structure, and the second transistor includes the second S/D structure. The method includes constructing a first electrical connection between gate structures of the first and second transistors and a second electrical connection between a third S/D structure of the first transistor and a fourth S/D structure of the second transistor.
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公开(公告)号：US11250923B2
公开(公告)日：2022-02-15
申请号：US17123039
申请日：2020-12-15
发明人： Meng-Sheng Chang , Yao-Jen Yang , Shao-Yu Chou , Yih Wang
摘要： A layout method includes: forming a layout structure of a memory array having a first row, wherein the first row comprises a plurality of storage cells; disposing a word line; disposing a plurality of control electrodes for connecting the plurality of storage cells of the first row to the word line; and disposing a first cut layer on a first portion of a first control electrode of the plurality of control electrodes.
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公开(公告)号：US11031407B2
公开(公告)日：2021-06-08
申请号：US16460266
申请日：2019-07-02
发明人： Min-Shin Wu , Meng-Sheng Chang , Shao-Yu Chou , Yao-Jen Yang
IPC分类号： G11C17/00 , H01L27/112 , G11C17/18 , G11C17/16
摘要： An IC device includes an anti-fuse device including a dielectric layer between a first gate structure and an active area, a first transistor including a second gate structure overlying the active area, and a second transistor including a third gate structure overlying the active area. The first gate structure is between the second gate structure and the third gate structure.
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公开(公告)号：US09425095B2
公开(公告)日：2016-08-23
申请号：US14720824
申请日：2015-05-24
发明人： You-Cheng Xiao , Yen-Huei Chen , Jung-Hsuan Chen , Shao-Yu Chou , Li-Chun Tien , Hung-Jen Liao
IPC分类号： H01L21/768 , H01L23/528 , H01L23/482 , H01L23/485 , H01L23/522
CPC分类号： H01L21/76879 , H01L21/768 , H01L21/76832 , H01L23/4824 , H01L23/485 , H01L23/522 , H01L23/528 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A system and method for a distributed metal routing is disclosed. An embodiment comprises a metal_0 layer with a metal_1 layer overlying the metal_0 layer. The metal_1 layer comprises separate parallel lines, with lines having different signals being distributed across the metal_1 layer. Such a layout decreases the parasitic resistance within the metal_0 layer as it decreases the distance current travels. Additionally, the distributed layout in metal_1 allows connections to be made to a metal_2 layer without the need for a hammer head connection of vias.
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公开(公告)号：US09401258B2
公开(公告)日：2016-07-26
申请号：US14446789
申请日：2014-07-30
发明人： Chen-Ming Hung , Yun-Han Chen , Shao-Tung Peng , Shao-Yu Chou , Yue-Der Chih , Li-Chun Tien
IPC分类号： H01H85/055
CPC分类号： H01H85/055 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure comprises a first conductive layer on a first level. The first conductive layer comprises a fuse line extending in a first direction. The fuse line has a first end portion, a second end portion opposite the first end portion, and a fuse link portion connecting the first end portion and the second end portion. The first conductive layer also comprises lines parallel to the fuse line, the lines being aligned in the first direction and being separated from one another by a first distance measured in the first direction. The fuse structure also comprises a second conductive layer on a second level different from the first level and coupled with the first conductive layer. The second conductive layer has parallel lines extending in a second direction, the parallel lines being separated by a second distance measured in a third direction orthogonal to the second direction.
摘要翻译： 熔丝结构包括在第一层上的第一导电层。 第一导电层包括沿第一方向延伸的熔丝线。 熔丝线具有第一端部，与第一端部相对的第二端部和连接第一端部和第二端部的熔断体部。 所述第一导电层还包括平行于所述熔丝线的线，所述线在所述第一方向上对齐并且在所述第一方向上测量的第一距离彼此分离。 熔丝结构还包括在与第一电平不同的第二电平上并与第一导电层耦合的第二导电层。 第二导电层具有沿第二方向延伸的平行线，平行线在与第二方向正交的第三方向上测量的第二距离分开。
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公开(公告)号：US20240146305A1
公开(公告)日：2024-05-02
申请号：US18170408
申请日：2023-02-16
发明人： Ting-Yu Yu , Meng-Sheng Chang , Shao-Yu Chou
IPC分类号： H03K19/0185 , H03K19/20
CPC分类号： H03K19/018521 , H03K19/20
摘要： The present disclosure includes a voltage provision circuit. In one aspect of the present disclosure, a voltage provision circuit is disclosed. The voltage provision circuit includes a first NMOS transistor gated with a first control signal and sourced with a ground voltage. The voltage provision circuit includes a second NMOS transistor gated with a second control signal complementary to the first control signal and sourced with the ground voltage. The voltage provision circuit includes a first PMOS transistor sourced with a first supply voltage. The voltage provision circuit includes a second PMOS transistor sourced with the first supply voltage. The voltage provision circuit includes a voltage modulation circuit, coupled between the first to second PMOS transistors and the first to second NMOS transistors, that is configured to provide a first intermediate signal based on the first and second control signals. In some embodiments, the first intermediate signal has a first logic state corresponding to the first supply voltage and a second logic state corresponding to a second supply voltage that is a fraction of the first supply voltage.
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公开(公告)号：US11783107B2
公开(公告)日：2023-10-10
申请号：US17178973
申请日：2021-02-18
发明人： Meng-Sheng Chang , Shao-Yu Chou , Yao-Jen Yang , Chen-Ming Hung
IPC分类号： G06F7/50 , G06F30/392 , G11C17/16 , G11C17/18 , H01L23/528 , H10B20/20 , H01L23/525
CPC分类号： G06F30/392 , G11C17/16 , G11C17/18 , H01L23/528 , H10B20/20 , H01L23/5252
摘要： An IC device includes a first anti-fuse structure including a first dielectric layer between a first gate conductor and a first active area, and a second anti-fuse structure including a second dielectric layer between a second gate conductor and the first active area. A first via is electrically connected to the first gate conductor at a first location a first distance from the first active area, a second via is electrically connected to the second gate conductor at a second location a second distance from the first active area, and the first distance is approximately equal to the second distance.
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公开(公告)号：US11621037B2
公开(公告)日：2023-04-04
申请号：US17375608
申请日：2021-07-14
发明人： Yuhsiang Chen , Shao-Yu Chou , Chun-Hao Chang , Min-Shin Wu , Yu-Der Chih
IPC分类号： G11C11/41 , G11C11/419 , G11C11/418 , G11C11/409 , G11C11/413 , G11C7/10
摘要： Memories are provided. A memory includes a first memory array, a second memory array and a read circuit. The first memory array is configured to store first data. The second memory array is configured to store second data that is complementary to the first data. The read circuit includes a decoding circuit, a sensing circuit and an output buffer. The decoding circuit is configured to provide a first signal according to the first data and a second signal according to the second data in response to an address signal. The sensing circuit is configured to provide a first sensing signal according to a reference signal and the first signal, and a second sensing signal according to the reference signal and the second signal. The output buffer is configured to provide the first sensing signal or the second sensing signal as an output according to a control signal.
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