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公开(公告)号：US20240363637A1
公开(公告)日：2024-10-31
申请号：US18771450
申请日：2024-07-12
发明人： Guo-Huei WU , Jerry Chang Jui KAO , Chih-Liang CHEN , Hui-Zhong ZHUANG , Jung-Chan YANG , Lee-Chung LU , Xiangdong CHEN
IPC分类号： H01L27/092 , H01L21/8238 , H01L23/528
CPC分类号： H01L27/0924 , H01L21/823821 , H01L21/823871 , H01L23/5286
摘要： A semiconductor device having a standard cell, includes a first power supply line, a second power supply line, a first gate-all-around field effect transistor (GAA FET) disposed over a substrate, and a second GAA FET disposed above the first GAA FET. The first power supply line and the second power supply line are located at vertically different levels from each other.
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公开(公告)号：US20240296273A1
公开(公告)日：2024-09-05
申请号：US18663652
申请日：2024-05-14
发明人： Jung-Chan YANG , Ting-Wei CHIANG , Jerry Chang-Jui KAO , Hui-Zhong ZHUANG , Lee-Chung LU , Li-Chun TIEN , Meng-Hung SHEN , Shang-Chih HSIEH , Chi-Yu LU
IPC分类号： G06F30/394 , H01L23/522 , H01L23/528 , H01L27/02 , H01L27/118
CPC分类号： G06F30/394 , H01L23/5226 , H01L23/5286 , H01L27/0207 , H01L27/11807 , H01L2027/11887
摘要： An integrated circuit includes a first power rail extending in a first direction, and configured to supply a first supply voltage, and a first region next to the first power rail. The first region includes a first conductive structure extending in the first direction, a first set of conductive structures extending in a second direction, and a first set of vias between the first set of conductive structures and the first conductive structure. The first set of conductive structures overlaps the first conductive structure and the first power rail, and is located on a second level. Each conductive structure of the first set of conductive structures is separated from each other in the first direction. Each via of the first set of vias is located where the first set of conductive structures overlaps the first conductive structure and couples the first set of conductive structures to the first conductive structure.
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公开(公告)号：US20230376672A1
公开(公告)日：2023-11-23
申请号：US18362946
申请日：2023-07-31
发明人： Hui-Zhong ZHUANG , Ting-Wei CHIANG , Li-Chun TIEN , Shun Li CHEN , Lee-Chung LU
IPC分类号： G06F30/398 , H01L27/02 , H01L27/118 , G06F30/392
CPC分类号： G06F30/398 , H01L27/0207 , H01L27/11807 , G06F30/392 , H01L2027/11881
摘要： An IC structure includes a first cell and a first and second rail. The first cell includes a first and second active region and a first, a second and a third gate structure. The first active region having a first dopant type. The second active region having a second dopant type. The first gate structure extending in a second direction, overlapping the first or the second active region. The second gate structure extending in the second direction, and overlapping a first edge of the first or second active region. The third gate structure extending in the second direction, and overlapping at least a second edge of the first or second active region. The first rail extending in the first direction and overlapping a middle portion of the first active region. The second rail extending in the first direction and overlapping a middle portion of the second active region.
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公开(公告)号：US20230253961A1
公开(公告)日：2023-08-10
申请号：US18302178
申请日：2023-04-18
发明人： Yung-Chen CHIEN , Xiangdong CHEN , Hui-Zhong ZHUANG , Tzu-Ying LIN , Jerry Chang Jui KAO , Lee-Chung LU
IPC分类号： H03K3/3562 , H03K3/037 , H03K3/012
CPC分类号： H03K3/35625 , H03K3/0372 , H03K3/012 , H03K3/0375
摘要： A flip-flop circuit includes a first inverter configured to receive a first clock signal and output a second clock signal, a second inverter configured to receive the second clock signal and output a third clock signal, a master stage, and a slave stage including a first feedback inverter and a first transmission gate. The first feedback inverter includes a first transistor configured to receive the first clock signal and a second transistor configured to receive the second clock signal, and the first transmission gate includes first and second input terminals configured to receive the second and third clock signals.
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公开(公告)号：US20230163066A1
公开(公告)日：2023-05-25
申请号：US18156711
申请日：2023-01-19
发明人： Ta-Pen GUO , Chien-Ying CHEN , Li-Chun TIEN , Lee-Chung LU
IPC分类号： H01L23/522 , G06F30/394
CPC分类号： H01L23/5226 , G06F30/394
摘要： A method of manufacturing a semiconductor device includes forming via structures in a first via layer over a transistor layer, the forming the via structures in the first via layer including forming a first via structure in the first via layer, the first via structure being included in a first deep via arrangement; forming conductive segments in a first metallization layer over the first via layer, the forming the conductive segments in the first metallization layer including forming M_1st routing segments at least a majority of which, relative to a first direction, have corresponding long axes with lengths which at least equal if not exceed a first permissible minimum value for routing segments in the first metallization layer; and forming an M_1st interconnection segment having a long axis which is less than the first permissible minimum value, the M_1st interconnection segment being included in the first deep via arrangement.
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公开(公告)号：US20220271025A1
公开(公告)日：2022-08-25
申请号：US17740328
申请日：2022-05-09
发明人： Chien-Ying CHEN , Lee-Chung LU , Li-Chun TIEN , Ta-Pen GUO
IPC分类号： H01L27/02 , H01L27/092 , G06F30/392
摘要： An IC device includes a first active area extending away from a first endpoint in a first direction, a second active area extending away from a second endpoint in the first direction, a third active area positioned between the first and second active areas, and a gate structure perpendicular to the first through third active areas. The gate structure overlies each of the first and second endpoints and the third active area, and the third active area extends away from the gate structure in a second direction opposite the first direction.
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公开(公告)号：US20210265987A1
公开(公告)日：2021-08-26
申请号：US17314370
申请日：2021-05-07
发明人： Kai-Chi HUANG , Yung-Chen CHIEN , Chi-Lin LIU , Wei-Hsiang MA , Jerry Chang Jui KAO , Shang-Chih HSIEH , Lee-Chung LU
IPC分类号： H03K3/037 , G06F1/3237 , H03K19/00 , H03K3/356
摘要： A circuit includes first and second power domains. The first power domain has a first power supply voltage level and includes a master latch, a first level shifter, and a slave latch coupled between the master latch and the first level shifter. The second power domain has a second power supply voltage level different from the first power supply voltage level and includes a retention latch coupled between the slave latch and the first level shifter, and the retention latch includes a second level shifter.
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公开(公告)号：US20200272778A1
公开(公告)日：2020-08-27
申请号：US15930010
申请日：2020-05-12
发明人： Chi-Lin LIU , Sheng-Hsiung CHEN , Jerry Chang-Jui KAO , Fong-Yuan CHANG , Lee-Chung LU , Shang-Chih HSIEH , Wei-Hsiang MA
IPC分类号： G06F30/327
摘要： A method includes: identifying ad hoc groups of elementary standard cells recurrent in a layout diagram, selecting one of the recurrent ad hoc groups (selected group) such that: the elementary standard cells in the selected group have connections representing a corresponding logic circuit; each elementary standard cell representing a logic gate; each ad hoc group has a number of transistors and a first number of logic gates; and the selected group providing a logical function. The method includes generating one or more macro standard cells such that: each macro standard cell has a number of transistors which is smaller than the number of transistors of the corresponding ad hoc group; or each macro standard cell has a second number of logic gates different than the first number of logic gates of the corresponding ad hoc group. The method also includes adding macro standard cells to the set of standard cells.
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公开(公告)号：US20200006335A1
公开(公告)日：2020-01-02
申请号：US16432024
申请日：2019-06-05
发明人： Hui-Zhong ZHUANG , Ting-Wei CHIANG , Chung-Te LIN , Lee-Chung LU , Li-Chun TIEN , Ting Yu CHEN
IPC分类号： H01L27/088 , H01L29/423 , H01L27/02 , G06F17/50
摘要： A semiconductor device includes fins extending substantially parallel to a first direction, at least one of the fins being a dummy fin; and at least one of the fins being an active fin; and at least one gate structure formed over corresponding ones of the fins and extending substantially parallel to a second direction, the second direction being substantially perpendicular to the first direction; wherein the fins and the at least one gate structure are located in a cell region which includes an odd number of fins. In an embodiment, the cell region is substantially rectangular and has first and second edges which are substantially parallel to the first direction; and neither of the first and second edges overlaps any of the fins.
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公开(公告)号：US20200006316A1
公开(公告)日：2020-01-02
申请号：US16204678
申请日：2018-11-29
发明人： Chien-Ying CHEN , Lee-Chung LU , Li-Chun TIEN , Ta-Pen GUO
IPC分类号： H01L27/02 , G06F17/50 , H01L27/092
摘要： A method of generating a layout diagram of an IC cell includes defining a boundary recess in a boundary of the cell by extending a first portion of the boundary along a first direction, extending a second portion of the boundary away from the first portion in a second direction perpendicular to the first direction, the second portion being contiguous with the first portion, and extending a third portion of the boundary away from the first portion in the second direction, the third portion being contiguous with the first portion. An active region is positioned in the cell by extending the active region away from the first portion in a third direction opposite to the second direction. The layout diagram is stored on a non-transitory computer-readable medium.
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