公开(公告)号：US20240363467A1

公开(公告)日：2024-10-31

申请号：US18140553

申请日：2023-04-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Jui-Wen SU ,  Shi-Hua TZENG ,  Chih-Hung LU ,  Po-Chi WU

IPC分类号： H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L27/06

CPC分类号： H01L23/3171 ,  H01L21/56 ,  H01L21/76804 ,  H01L27/0629

摘要： In order to reduce the incidence of stress concentration areas in an etched opening, a thinner polyimide layer is deposited to minimize gap formation therein, and a descum process is then performed to increase the angle of the presented layer surface. Reduction of the stress in this manner reduces the incidence of cracking of the later formed metal contact, which improves the overall pass rates of semiconductor devices so manufactured.

公开(公告)号：US20150048516A1

公开(公告)日：2015-02-19

申请号：US13969324

申请日：2013-08-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Hung LU ,  Ching-Chen HAO

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L21/76831 ,  H01L21/02123 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/31116 ,  H01L21/76808 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit that includes a substrate, a metal layer over the substrate and a first dielectric layer over the metal layer. The first dielectric layer includes a via. A sidewall layer that includes a silicon compound is in the via. A second dielectric layer is over the sidewall layer and an ultra-thick metal (UTM) layer is in the via.

摘要翻译： 一种集成电路，其包括衬底，在所述衬底上的金属层和所述金属层上的第一电介质层。 第一电介质层包括通孔。 包含硅化合物的侧壁层在通孔中。 第二电介质层在侧壁层上方，超厚金属（UTM）层位于通孔中。

公开(公告)号：US20230411279A1

公开(公告)日：2023-12-21

申请号：US17845515

申请日：2022-06-21

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Liang-Hsuan PENG ,  Chih-Hung LU ,  Chih-Lin WANG ,  Song-Bor LEE

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76802 ,  H01L21/76829

摘要： A semiconductor device structure, along with methods of forming such, are described. The structure includes an interconnect structure disposed over a substrate, a first conductive feature disposed in the interconnect structure, a dielectric layer disposed on the interconnect structure, and a second conductive feature having a top portion and a bottom portion. The top portion is disposed over the dielectric layer, and the bottom portion is disposed through the dielectric layer. The structure further includes an adhesion layer disposed over the dielectric layer and the second conductive feature. The adhesion layer includes a first portion disposed on a top of the second conductive feature and a second portion disposed over the dielectric layer, the first portion has a thickness, and the second portion has a width substantially greater than the thickness.

公开(公告)号：US20170069530A1

公开(公告)日：2017-03-09

申请号：US15356174

申请日：2016-11-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Hung LU ,  Ching-Chen HAO

IPC分类号： H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/76831 ,  H01L21/02123 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/31116 ,  H01L21/76808 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming an integrated circuit that includes providing a substrate, a metal layer over the substrate, and a first dielectric layer over the metal layer. The first dielectric layer includes a via. A sidewall layer that includes a silicon compound is in the via. A second dielectric layer is over the sidewall layer and an ultra-thick metal (UTM) layer is in the via.

摘要翻译： 一种形成集成电路的方法，包括提供衬底，在衬底上的金属层，以及金属层上的第一电介质层。 第一电介质层包括通孔。 包含硅化合物的侧壁层在通孔中。 第二电介质层在侧壁层上方，超厚金属（UTM）层位于通孔中。