公开(公告)号：US20200185440A1

公开(公告)日：2020-06-11

申请号：US16790386

申请日：2020-02-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chia-Yu WEI ,  Fu-Cheng CHANG ,  Hsin-Chi CHEN ,  Ching-Hung KAO ,  Chia-Pin CHENG ,  Kuo-Cheng LEE ,  Hsun-Ying HUANG ,  Yen-Liang LIN

IPC分类号： H01L27/146 ,  H01L29/423 ,  H01L29/06 ,  H01L29/78

摘要： A gate structure includes a gate and a first isolation structure having a top surface and a bottom surface. The gate includes a first sidewall adjacent to the first isolation structure, a second sidewall, a first horizontal surface adjacent to a bottom edge of the first sidewall and a bottom edge of the second sidewall, the first horizontal surface being between the top surface of the first isolation structure and the bottom surface of the first isolation structure. The gate also includes a second horizontal surface adjacent to a top edge of the second sidewall. An effective channel width defined by the gate structure includes a height of the second sidewall and a width of the second horizontal surface.

公开(公告)号：US20220293650A1

公开(公告)日：2022-09-15

申请号：US17830707

申请日：2022-06-02

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chia-Yu WEI ,  Fu-Cheng CHANG ,  Hsin-Chi CHEN ,  Ching-Hung KAO ,  Chia-Pin CHENG ,  Kuo-Cheng LEE ,  Hsun-Ying HUANG ,  Yen-Liang LIN

IPC分类号： H01L27/146 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06

摘要： A semiconductor device includes a plurality of isolation structures, wherein each isolation structure of the plurality of isolation structures is spaced from an adjacent isolation structure of the plurality of isolation structures in a first direction. The semiconductor device further includes a gate structure. The gate structure includes a top surface; a first sidewall angled at a non-perpendicular angle with respect to the top surface; and a second sidewall angled with respect to the top surface. The gate structure further includes a first horizontal surface extending between the first sidewall and the second sidewall, wherein the first horizontal surface is parallel to the top surface, and a dimension of the gate structure in a second direction, perpendicular to the first direction, is less than a dimension of each of the plurality of isolation structures in the second direction.

公开(公告)号：US20180166481A1

公开(公告)日：2018-06-14

申请号：US15591689

申请日：2017-05-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chia-Yu WEI ,  Fu-Cheng CHANG ,  Hsin-Chi CHEN ,  Ching-Hung KAO ,  Chia-Pin CHENG ,  Kuo-Cheng LEE ,  Hsun-Ying HUANG ,  Yen-Liang LIN

IPC分类号： H01L27/146 ,  H01L29/06 ,  H01L27/088 ,  H01L29/40 ,  H01L29/423

摘要： A gate structure includes a gate and a first isolation structure having a top surface and a bottom surface. The gate includes a first sidewall adjacent to the first isolation structure, a second sidewall, a first horizontal surface adjacent to a bottom edge of the first sidewall and a bottom edge of the second sidewall, the first horizontal surface being between the top surface of the first isolation structure and the bottom surface of the first isolation structure. The gate also includes a second horizontal surface adjacent to a top edge of the second sidewall. An effective channel width defined by the gate structure includes a height of the second sidewall and a width of the second horizontal surface.

公开(公告)号：US20240038719A1

公开(公告)日：2024-02-01

申请号：US17816055

申请日：2022-07-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wen-Ting LAN ,  I-Han HUANG ,  Fu-Cheng CHANG ,  Lin-Yu HUANG ,  Shi-Ning JU ,  Kuo-Cheng CHIANG

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L21/02 ,  H01L21/265 ,  H01L23/498 ,  H01L23/538

CPC分类号： H01L24/83 ,  H01L24/32 ,  H01L25/0657 ,  H01L24/29 ,  H01L21/0245 ,  H01L21/26533 ,  H01L24/16 ,  H01L23/49894 ,  H01L23/49838 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5386 ,  H01L23/5389 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06517 ,  H01L2225/06593 ,  H01L2924/37001 ,  H01L2224/29187 ,  H01L2224/83005 ,  H01L2224/8313 ,  H01L2224/83123 ,  H01L2224/8383 ,  H01L2224/32145 ,  H01L2224/16227 ,  H01L21/4857

摘要： A method of forming a semiconductor structure is provided. Two wafers are first bonded by oxide bonding. Next, the thickness of a first wafer is reduced using an ion implantation and separation approach, and a second wafer is thinned by using a removal process. First devices are formed on the first wafer, and a carrier is then attached over the first wafer, and an alignment process is performed from the bottom of the second wafer to align active regions of the second wafer for placement of the second devices with active regions of the first wafer for placement of the first devices. The second devices are then formed in the active regions of the second wafer. Furthermore, a via structure is formed through the first wafer, the second wafer and the insulation layer therebetween to connect the first and second devices on the two sides of the insulation layer.

公开(公告)号：US20230378205A1

公开(公告)日：2023-11-23

申请号：US18362507

申请日：2023-07-31

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chia-Yu WEI ,  Fu-Cheng CHANG ,  Hsin-Chi CHEN ,  Ching-Hung KAO ,  Chia-Pin CHENG ,  Kuo-Cheng LEE ,  Hsun-Ying HUANG ,  Yen-Liang LIN

IPC分类号： H01L27/146 ,  H01L29/423 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L27/14614 ,  H01L27/14643 ,  H01L29/42376 ,  H01L29/0653 ,  H01L29/7853 ,  H01L29/4236 ,  H01L29/78

摘要： A semiconductor device includes a plurality of isolation structures, wherein each isolation structure of the plurality of isolation structures is spaced from an adjacent isolation structure of the plurality of isolation structures. The semiconductor device further includes a gate structure. The gate structure includes a first sidewall and a second sidewall angled with respect to the first sidewall. The gate structure further includes a first surface extending between the first sidewall and the second sidewall, wherein a dimension of the gate structure in a first direction is less than a dimension of each of the plurality of isolation structures in the first direction.

公开(公告)号：US20230299104A1

公开(公告)日：2023-09-21

申请号：US18319159

申请日：2023-05-17

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Po-Han CHEN ,  Chen-Chun CHEN ,  Fu-Cheng CHANG ,  Kuo-Cheng LEE

IPC分类号： H01L27/146

CPC分类号： H01L27/14623 ,  H01L27/14685 ,  H01L27/14605

摘要： A method of making an image sensor includes depositing a shield layer over a substrate, wherein the substrate comprises a first photodiode (PD) and a second PD. The method further includes etching the shield layer to define a first recess aligned with the first PD and a second recess aligned with the second PD. The method further includes depositing a flicker reduction layer in the first recess and in the second recess. The method further includes etching the flicker reduction layer to remove the flicker reduction layer from the first recess.