公开(公告)号：US20190067264A1

公开(公告)日：2019-02-28

申请号：US15904959

申请日：2018-02-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hidehiro FUJIWARA ,  Hung-Jen LIAO ,  Hsien-Yu PAN ,  Chih-Yu LIN ,  Yen-Huei CHEN ,  Sahil Preet SINGH

IPC分类号： H01L27/02 ,  H01L27/11

摘要： A memory array includes a column of cells arranged along a first direction and a bit line extending along the first direction over the column of cells. The column of cells includes a set of memory cells and a set of strap cells. The bit line includes a first conductor in a second conductor. The first conductor extends in the first direction and is in a first conductive layer. The second conductor extends in the first direction and is in a second conductive layer different from the first conductive layer.

公开(公告)号：US20240357788A1

公开(公告)日：2024-10-24

申请号：US18756363

申请日：2024-06-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hidehiro FUJIWARA ,  Chih-Yu LIN ,  Hsien-Yu PAN ,  Yasutoshi OKUNO ,  Yen-Huei CHEN ,  Hung-Jen LIAO

IPC分类号： H10B10/00 ,  G06F30/392 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02

CPC分类号： H10B10/12 ,  G06F30/392 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/0207

摘要： A memory circuit includes a first pull down transistor, a first pass gate transistor coupled to the first pull down transistor, a second pull down transistor, a second pass gate transistor and a first metal contact. The second pull down transistor has a first active region located on a first level. The second pass gate transistor has a second active region located on the first level, and being coupled to the second pull down transistor. The first metal contact extends from the first active region to the second active region, being located on a second level, and electrically coupling a drain of the second pull down transistor to a drain of the second pass gate transistor. The first pass gate transistor, the second pass gate transistor, the first pull down transistor and the second pull down transistor are part of a four transistor (4T) memory cell.

公开(公告)号：US20210217742A1

公开(公告)日：2021-07-15

申请号：US17213074

申请日：2021-03-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hidehiro FUJIWARA ,  Sahil Preet SINGH ,  Chih-Yu LIN ,  Hsien-Yu PAN ,  Yen-Huei CHEN ,  Hung-Jen LIAO

IPC分类号： H01L27/02 ,  H01L27/11 ,  H01L23/522 ,  G11C5/06 ,  G11C7/18

摘要： A memory array includes a first memory cell configured to store data, a second memory cell configured to store data and a bit line extending along the first direction, and being over the first memory cell and the second memory cell. The first memory cell and the second memory cell are arranged along a first direction in a first column of memory cells. The bit line includes a first conductor extending in the first direction and being in a first conductive layer, and a second conductor extending in the first direction and being in a second conductive layer different from the first conductive layer.

公开(公告)号：US20230301049A1

公开(公告)日：2023-09-21

申请号：US18304301

申请日：2023-04-20

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hidehiro FUJIWARA ,  Chih-Yu LIN ,  Hsien-Yu PAN ,  Yasutoshi OKUNO ,  Yen-Huei CHEN ,  Hung-Jen LIAO

IPC分类号： H10B10/00 ,  H01L23/528 ,  H01L27/02 ,  H01L23/522 ,  G06F30/392

CPC分类号： H10B10/12 ,  G06F30/392 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/0207

摘要： A method of forming a memory circuit includes generating a layout design of the memory circuit, and manufacturing the memory circuit based on the layout design. The generating of the layout design includes generating a first active region layout pattern corresponding to fabricating a first active region of a first pull down transistor, generating a second active region layout pattern corresponding to fabricating a second active region of a first pass gate transistor, and generating a first metal contact layout pattern corresponding to fabricating a first metal contact. The first metal contact layout pattern overlaps the cell boundary of the memory circuit and the first active region layout pattern. The first metal contact electrically coupled to a source of the first pull down transistor. The memory circuit being a four transistor (4T) memory cell including a first and second pass gate transistor, and a first and second pull down transistor.

公开(公告)号：US20240363616A1

公开(公告)日：2024-10-31

申请号：US18769004

申请日：2024-07-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hidehiro FUJIWARA ,  Sahil Preet SINGH ,  Chih-Yu LIN ,  Hsien-Yu PAN ,  Yen-Huei CHEN ,  Hung-Jen LIAO

IPC分类号： H01L27/02 ,  G11C5/06 ,  G11C7/18 ,  H01L23/522 ,  H10B10/00

CPC分类号： H01L27/0207 ,  G11C5/063 ,  G11C7/18 ,  H01L23/5226 ,  H10B10/12

摘要： A memory array includes a first memory cell configured to store data, a second memory cell configured to store data and a bit line extending along the first direction, and being over the first memory cell and the second memory cell. The first memory cell and the second memory cell are arranged along a first direction in a first column of memory cells. The bit line includes a first conductor extending in the first direction and being in a first conductive layer, and a second conductor extending in the first direction and being in a second conductive layer different from the first conductive layer.

公开(公告)号：US20210272967A1

公开(公告)日：2021-09-02

申请号：US17325641

申请日：2021-05-20

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hidehiro FUJIWARA ,  Chih-Yu LIN ,  Hsien-Yu PAN ,  Yasutoshi OKUNO ,  Yen-Huei CHEN ,  Hung-Jen LIAO

IPC分类号： H01L27/11 ,  H01L23/528 ,  H01L27/02 ,  H01L23/522 ,  G06F30/392

摘要： A method of forming a memory circuit includes generating a layout design of the memory circuit, and manufacturing the memory circuit based on the layout design. The memory circuit is a four transistor memory cell that includes at least the first pass gate transistor and the first pull up transistor. The generating of the layout design includes generating a first active region layout pattern corresponding to fabricating a first active region of a first pull up transistor, generating a second active region layout pattern corresponding to fabricating a second active region of a first pass gate transistor, and generating a first metal contact layout pattern corresponding to fabricating a first metal contact is electrically coupled to a source of the first pull up transistor. The first metal contact layout pattern extends in a second direction, overlaps a cell boundary of the memory circuit and the first active region layout pattern.

公开(公告)号：US20200020699A1

公开(公告)日：2020-01-16

申请号：US16457553

申请日：2019-06-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hidehiro FUJIWARA ,  Hung-Jen LIAO ,  Hsien-Yu PAN ,  Chih-Yu LIN ,  Yen-Huei CHEN ,  Yasutoshi OKUNO

IPC分类号： H01L27/11 ,  H01L23/528 ,  H01L23/522 ,  H01L27/02 ,  G06F17/50

摘要： A memory cell includes a first and second pull up transistor, a first and second pass gate transistor and a metal contact. The first pull up transistor has a first active region extending in a first direction. The first pass gate transistor has a second active region extending in the first direction, and being separated from the first active region in a second direction. The second active region is adjacent to the first active region. The second pass gate transistor is coupled to the second pull up transistor. The metal contact extends in the second direction, and extends from the first active region to the second active region. The metal contact couples drains of the first pull up transistor and the first pass gate transistor. The first and second pass gate transistors and the first and second pull up transistors are part of a four transistor memory cell.