公开(公告)号：US20240381664A1

公开(公告)日：2024-11-14

申请号：US18784089

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yi Yang WEI ,  Tzu-Yu LIN ,  Bi-Shen LEE ,  Hai-Dang TRINH ,  Hsing-Lien LIN ,  Hsun-Chung KUANG

IPC: H10B53/30

Abstract: Ferroelectric stacks are disclosed herein that can improve retention performance of ferroelectric memory devices. An exemplary ferroelectric stack has a ferroelectric switching layer (FSL) stack disposed between a first electrode and a second electrode. The ferroelectric stack includes a barrier layer disposed between a first FSL and a second FSL, where a first crystalline condition of the barrier layer is different than a second crystalline condition of the first FSL and/or the second FSL. In some embodiments, the first crystalline condition is an amorphous phase, and the second crystalline condition is an orthorhombic phase. In some embodiments, the first FSL and/or the second FSL include a first metal oxide, and the barrier layer includes a second metal oxide. The ferroelectric stack can be a ferroelectric capacitor, a portion of a transistor, and/or connected to a transistor in a ferroelectric memory device to provide data storage in a non-volatile manner.

公开(公告)号：US20240332026A1

公开(公告)日：2024-10-03

申请号：US18326494

申请日：2023-05-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chi-Fan CHEN ,  Chun-Kai LAN ,  Zhen Yu GUAN ,  Hsun-Chung KUANG ,  Cheng-Yuan TSAI ,  Chung-Yi YU

IPC: H01L21/306 ,  B24B37/04 ,  B24B37/16

CPC classification number: H01L21/30625 ,  B24B37/042 ,  B24B37/16

Abstract: A substrate grinding tool is configured to remove material from a semiconductor substrate in a grinding operation. In the grinding operation, the substrate grinding tool uses a combination of mechanical grinding and a chemical etchant to remove material from the semiconductor substrate. The chemical etchant may be heated to a high temperature, which may increase the etch rate of the chemical etchant. The use of the combination of mechanical grinding and the chemical etchant may increase the grinding rate of the substrate grinding tool for grinding semiconductor substrates, may reduce surface roughness for semiconductor substrates that are processed by the substrate grinding tool, and/or may reduce surface damage for semiconductor substrates that are processed by the substrate grinding tool, among other examples.

公开(公告)号：US20230402487A1

公开(公告)日：2023-12-14

申请号：US17838994

申请日：2022-06-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Bi-Shen LEE ,  Chia-Wei HU ,  Hai-Dang TRINH ,  Min-Ying TSAI ,  Ching I LI ,  Hsun-Chung KUANG ,  Cheng-Yuan TSAI

IPC: H01L27/146

CPC classification number: H01L27/14698 ,  H01L27/14645 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14685

Abstract: A Deep Trench Isolation (DTI) structure is disclosed. The DTI structures according to embodiments of the present disclosure include a composite passivation layer. In some embodiments, the composite passivation layer includes a hole accumulation layer and a defect repairing layer. The defect repairing layer is disposed between the hole accumulation layer and a semiconductor substrate in which the DTI structure is formed. The defect repairing layer reduces lattice defects in the interface, thus, reducing the density of interface trap (DIT) at the interface. Reduced density of interface trap facilitates strong hole accumulation, thus increasing the flat band voltage. In some embodiments, the hole accumulation layer according to the present disclosure is enhanced by an oxidization treatment.

公开(公告)号：US20210327748A1

公开(公告)日：2021-10-21

申请号：US17360784

申请日：2021-06-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Tsai-Ming HUANG ,  Wei-Chieh HUANG ,  Hsun-Chung KUANG ,  Yen-Chang CHU ,  Cheng-Che CHUNG ,  Chin-Wei LIANG ,  Ching-Sen KUO ,  Jieh-Jang CHEN ,  Feng-Jia SHIU ,  Sheng-Chau CHEN

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/321 ,  H01L23/544 ,  H01L23/522

Abstract: In a method of manufacturing a semiconductor device, a first interlayer dielectric (ILD) layer is formed over a substrate, a chemical mechanical polishing (CMP) stop layer is formed over the first ILD layer, a trench is formed by patterning the CMP stop layer and the first ILD layer, a metal layer is formed over the CMP stop layer and in the trench, a sacrificial layer is formed over the metal layer, a CMP operation is performed on the sacrificial layer and the metal layer to remove a portion of the metal layer over the CMP stop layer, and a remaining portion of the sacrificial layer over the trench is removed.

公开(公告)号：US20240404877A1

公开(公告)日：2024-12-05

申请号：US18784282

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tsai-Ming HUANG ,  Wei-Chieh HUANG ,  Hsun-Chung KUANG ,  Yen-Chang CHU ,  Cheng-Che CHUNG ,  Chin-Wei LIANG ,  Ching-Sen KUO ,  Jieh-Jang CHEN ,  Feng-Jia SHIU ,  Sheng-Chau CHEN

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/321 ,  H01L23/522 ,  H01L23/544

Abstract: In a method of manufacturing a semiconductor device, a first interlayer dielectric (ILD) layer is formed over a substrate, a chemical mechanical polishing (CMP) stop layer is formed over the first ILD layer, a trench is formed by patterning the CMP stop layer and the first ILD layer, a metal layer is formed over the CMP stop layer and in the trench, a sacrificial layer is formed over the metal layer, a CMP operation is performed on the sacrificial layer and the metal layer to remove a portion of the metal layer over the CMP stop layer, and a remaining portion of the sacrificial layer over the trench is removed.