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公开(公告)号：US20240371666A1
公开(公告)日：2024-11-07
申请号：US18348546
申请日：2023-07-07
Inventor： Hau-Yi HSIAO , Kuo-Ming WU , Sheng-Chau CHEN , Ru-Liang LEE
Abstract: Some implementations herein provide for a system and methods for in-line monitoring of a sealant being dispensed by a jet nozzle in a beveled region along a perimeter of a stack of semiconductor substrates. The system includes an automated optical inspection system. During the dispensing of the sealant by the jet nozzle, the automated optical inspection system may monitor an amount of an accumulation of the sealant within the beveled region.
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公开(公告)号：US20230268367A1
公开(公告)日：2023-08-24
申请号：US18308698
申请日：2023-04-28
Inventor： Tsung-Wei HUANG , Chao-Ching CHANG , Yun-Wei CHENG , Chih-Lung CHENG , Yen-Chang CHEN , Wen-Jen TSAI , Cheng Han LIN , Yu-Hsun CHIH , Sheng-Chan LI , Sheng-Chau CHEN
IPC: H01L27/146
CPC classification number: H01L27/1463 , H01L27/14621 , H01L27/14627 , H01L27/14645 , H01L27/14685 , H01L27/14689
Abstract: An isolation structure can be formed between adjacent and/or non-adjacent pixel regions (e.g., between diagonal or cross-road pixel regions), of an image sensor, to reduce and/or prevent optical crosstalk. The isolation structure may include a deep trench isolation (DTI) structure or another type of trench that is partially filled with a material such that an air gap is formed therein. The DTI structure having the air gap formed therein may reduce optical crosstalk between pixel regions. The reduced optical crosstalk may increase spatial resolution of the image sensor, may increase overall sensitivity of the image sensor, may decrease color mixing between pixel regions of the image sensor, and/or may decrease image noise after color correction of images captured using the image sensor.
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公开(公告)号：US20240404877A1
公开(公告)日：2024-12-05
申请号：US18784282
申请日：2024-07-25
Inventor： Tsai-Ming HUANG , Wei-Chieh HUANG , Hsun-Chung KUANG , Yen-Chang CHU , Cheng-Che CHUNG , Chin-Wei LIANG , Ching-Sen KUO , Jieh-Jang CHEN , Feng-Jia SHIU , Sheng-Chau CHEN
IPC: H01L21/768 , H01L21/02 , H01L21/3105 , H01L21/321 , H01L23/522 , H01L23/544
Abstract: In a method of manufacturing a semiconductor device, a first interlayer dielectric (ILD) layer is formed over a substrate, a chemical mechanical polishing (CMP) stop layer is formed over the first ILD layer, a trench is formed by patterning the CMP stop layer and the first ILD layer, a metal layer is formed over the CMP stop layer and in the trench, a sacrificial layer is formed over the metal layer, a CMP operation is performed on the sacrificial layer and the metal layer to remove a portion of the metal layer over the CMP stop layer, and a remaining portion of the sacrificial layer over the trench is removed.
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公开(公告)号：US20240030259A1
公开(公告)日：2024-01-25
申请号：US17870354
申请日：2022-07-21
Inventor： Chung-Liang CHENG , Sheng-Chau CHEN , Chung-Yi YU , Cheng-Yuan TSAI
IPC: H01L27/146
CPC classification number: H01L27/1463 , H01L27/14683
Abstract: Doping a liner of a trench isolation structure with zinc and/or gallium reduces dark current from a photodiode. For example, the zinc and/or gallium may be deposited on a temporary oxide layer and driven into a high-k layer surrounding a deep trench isolation structure and an interface between the high-k layer and surrounding silicon. In another example, the zinc and/or gallium may be deposited on an oxide layer between the high-k layer and surrounding silicon. As a result, sensitivity of the photodiode is increased. Additionally, breakdown voltage of the photodiode is increased, and a quantity of white pixels in a pixel array including the photodiode are reduced.
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公开(公告)号：US20240316724A1
公开(公告)日：2024-09-26
申请号：US18187464
申请日：2023-03-21
Inventor： Hau-Yi HSIAO , Kuo-Ming WU , Sheng-Chau CHEN
Abstract: Some implementations herein describe a chemical-mechanical planarization tool including a polishing pad. The chemical-mechanical planarization tool including the polishing pad may perform a polishing operation to a semiconductor substrate. The polishing operation may generate, along a perimeter of the semiconductor substrate, a roll-off profile that satisfies a threshold. The polishing pad includes two or more regions, where each region includes a different pad surface pattern. Each region including a different pad surface pattern may correspond to a different polishing rate. Techniques using the polishing pad having such zone and pad surface pattern combinations allow for a focused and a controlled polishing of the semiconductor substrate, including along the perimeter of the semiconductor substrate to tightly control the roll-off profile.
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Patent Agency Ranking
公开(公告)号：US20240084455A1
公开(公告)日：2024-03-14
申请号：US18166196
申请日：2023-02-08
Inventor： Che Wei YANG , Chih Cheng SHIH , Kuo Liang LU , Yu JIANG , Sheng-Chan LI , Kuo-Ming WU , Sheng-Chau CHEN , Chung-Yi YU , Cheng-Yuan TSAI
CPC classification number: C23C16/50 , C23C16/405 , C23C16/56 , H01J37/32541 , H01J37/32568 , H01J2237/3321
Abstract: Some implementations described herein include systems and techniques for fabricating a wafer-on-wafer product using a filled lateral gap between beveled regions of wafers included in a stacked-wafer assembly and along a perimeter region of the stacked-wafer assembly. The systems and techniques include a deposition tool having an electrode with a protrusion that enhances an electromagnetic field along the perimeter region of the stacked-wafer assembly during a deposition operation performed by the deposition tool. Relative to an electromagnetic field generated by a deposition tool not including the electrode with the protrusion, the enhanced electromagnetic field improves the deposition operation so that a supporting fill material may be sufficiently deposited.
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公开(公告)号：US20230411227A1
公开(公告)日：2023-12-21
申请号：US17807640
申请日：2022-06-17
Inventor： I-Nan. CHEN , Kuo-Ming WU , Ming-Che LEE , Hau-Yi HSIAO , Yung-Lung LIN , Che Wei YANG , Sheng-Chau CHEN
IPC: H01L21/66 , H01L21/3105 , G05B19/416
CPC classification number: H01L22/26 , H01L21/31053 , G05B19/416 , G05B2219/45232
Abstract: Some implementations described herein provide techniques and apparatuses for polishing a perimeter region of a semiconductor substrate so that a roll-off profile at or near the perimeter region of the semiconductor substrate satisfies a threshold. The described implementations include depositing a first layer of a first oxide material across the semiconductor substrate followed by depositing a second layer of a second oxide material over the first layer of the first oxide material and around a perimeter region of the semiconductor substrate. The described implementations further include polishing the second layer of the second oxide material over the perimeter region using a chemical mechanical planarization tool including one or more ring-shaped polishing pads oriented vertically over the perimeter region.
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公开(公告)号：US20240339422A1
公开(公告)日：2024-10-10
申请号：US18298064
申请日：2023-04-10
Inventor： Che Wei YANG , Kuo-Ming WU , Sheng-Chau CHEN , Cheng-Yuan TSAI , Hau-Yi HSIAO , Chung-Yi YU
IPC: H01L23/00
CPC classification number: H01L24/08 , H01L23/562 , H01L24/03 , H01L24/80 , H01L24/06 , H01L2224/02235 , H01L2224/0226 , H01L2224/03011 , H01L2224/05611 , H01L2224/05639 , H01L2224/05644 , H01L2224/05655 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896
Abstract: Some implementations described herein provide techniques and apparatuses for forming a stacked die product including two or more integrated circuit dies. A bond interface between two integrated circuit dies that are included in the stacked die product includes a layered structure. As part of the layered structure, respective layers of a sealant material are directly on co-facing surfaces of the two integrated circuit dies. The layered structure further includes one or more bonding layers between the respective layers of the sealant material that are directly on the co-facing surfaces of the two integrated circuit dies. The layered structure may reduce lateral stresses throughout the bond interface to reduce a likelihood of warpage of the two integrated circuit dies.
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公开(公告)号：US20240030258A1
公开(公告)日：2024-01-25
申请号：US17814347
申请日：2022-07-22
Inventor： Chung-Liang CHENG , Sheng-Chan LI , Sheng-Chau CHEN , Chung-Yi YU , Cheng-Yuan TSAI
IPC: H01L27/146
CPC classification number: H01L27/1463 , H01L27/14645 , H01L27/14621 , H01L27/14627 , H01L27/14689
Abstract: Doping a liner of a trench isolation structure with fluorine reduces dark current from a photodiode. For example, the fluorine may be added to a passivation layer surrounding a backside deep trench isolation structure. As a result, sensitivity of the photodiode is increased. Additionally, breakdown voltage of the photodiode is increased, and a quantity of white pixels in a pixel array including the photodiode are reduced.
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公开(公告)号：US20240421066A1
公开(公告)日：2024-12-19
申请号：US18335838
申请日：2023-06-15
Inventor： Chung-Liang CHENG , Sheng-Chau CHEN
IPC: H01L23/522 , H01L21/768 , H01L23/532
Abstract: Forming a barrier layer and removing the barrier layer from an upper portion of a recess in which a metal-insulator-metal (MIM) structure will be formed allows for forming the MIM structure with fewer voids, which improves capacitance of the MIM structure. For example, a bottom layer anti-reflective coating may be deposited and etched back in order to allow for removal of the barrier layer from the upper portion of the recess but not from a bottom portion of the recess. Additionally, the barrier layer may be formed using physical vapor deposition, which reduces carbon impurities in the barrier layer as compared with using atomic layer deposition, which improves resistance for the MIM structure.
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