公开(公告)号：US12125848B2

公开(公告)日：2024-10-22

申请号：US18132924

申请日：2023-04-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Ching Wang ,  Chun-Chung Su ,  Chung-Wei Wu ,  Jon-Hsu Ho ,  Kuan-Lun Cheng ,  Wen-Hsing Hsieh ,  Wen-Yuan Chen ,  Zhi-Qiang Wu

IPC分类号： H01L27/088 ,  H01L21/764 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L27/088 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66742

摘要： A semiconductor device structure includes a dielectric layer, a first source/drain feature in contact with the dielectric layer, wherein the first source/drain feature comprises a first sidewall. The structure also includes a second source/drain feature in contact with the dielectric layer and adjacent to the first source/drain feature, wherein the second source/drain feature comprises a second sidewall. The structure also includes an insulating layer disposed over the dielectric layer and between the first sidewall and the second sidewall, wherein the insulating layer comprises a first surface facing the first sidewall, a second surface facing the second sidewall, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The structure further includes a sealing material disposed between the first sidewall and the first surface, wherein the sealing material, the first sidewall, the first surface, and the dielectric layer are exposed to an air gap.

公开(公告)号：US11626400B2

公开(公告)日：2023-04-11

申请号：US17377796

申请日：2021-07-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Ching Wang ,  Wen-Yuan Chen ,  Chun Chung Su ,  Jon-Hsu Ho ,  Wen-Hsing Hsieh ,  Kuan-Lun Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC分类号： H01L27/088 ,  H01L21/764 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66

摘要： A semiconductor device structure includes a dielectric layer, a first source/drain feature in contact with the dielectric layer, wherein the first source/drain feature comprises a first sidewall, and a second source/drain feature in contact with the dielectric layer and adjacent to the first source/drain feature, wherein the second source/drain feature comprises a second sidewall. The structure also includes an insulating layer disposed over the dielectric layer and between the first sidewall and the second sidewall, wherein the insulating layer comprises a first surface facing the first sidewall, a second surface facing the second sidewall, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The structure includes a sealing material disposed between the first sidewall and the first surface, wherein the sealing material, the first sidewall, the first surface, and the dielectric layer are exposed to an air gap.

公开(公告)号：US08765533B2

公开(公告)日：2014-07-01

申请号：US13693685

申请日：2012-12-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd

发明人： Wen-Hsing Hsieh ,  Zhiqiang Wu ,  Ching-Fang Huang ,  Jon-Hsu Ho

IPC分类号： H01L21/8238

CPC分类号： H01L29/66545 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/7853

摘要： A FinFET device and method for fabricating a FinFET device are disclosed. An exemplary method includes providing a substrate; forming a fin over the substrate; forming an isolation feature over substrate; forming a gate structure including a dummy gate over a portion of the fin, the gate structure traversing the fin, wherein the gate structure separates a source region and a drain region of the fin, a channel being defined in the portion of the fin between the source region and the drain region; and replacing the dummy gate of the gate structure with a metal gate, wherein during the replacing the dummy gate, a profile of the portion of the fin is modified. In an example, modifying the profile of the portion of the fin includes increasing a height of the portion of the fin and/or decreasing a width of the portion of the fin.

摘要翻译： 公开了一种用于制造FinFET器件的FinFET器件和方法。 一种示例性方法包括提供基底; 在基板上形成翅片; 在衬底上形成隔离特征; 在所述鳍片的一部分上形成包括虚拟栅极的栅极结构，所述栅极结构穿过所述鳍片，其中所述栅极结构分离所述鳍片的源极区域和漏极区域，在所述鳍片的所述部分中限定的沟道 源区和漏区; 并且用金属栅极替换栅极结构的虚拟栅极，其中在更换伪栅极期间改变鳍部分的轮廓。 在一个实例中，修改翅片部分的轮廓包括增加翅片部分的高度和/或减小翼片的该部分的宽度。

公开(公告)号：US20230387240A1

公开(公告)日：2023-11-30

申请号：US18447183

申请日：2023-08-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Ching Wang ,  Chung-I Yang ,  Jon-Hsu Ho ,  Wen-Hsing Hsieh ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC分类号： H01L29/45 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/285 ,  H01L21/306 ,  H01L21/764 ,  H01L21/02

CPC分类号： H01L29/45 ,  H01L29/0653 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/0259 ,  H01L21/28518 ,  H01L21/30604 ,  H01L21/764 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66553 ,  H01L29/66742

摘要： Source/drain silicide that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a first channel layer disposed over a substrate, a second channel layer disposed over the first channel layer, and a gate stack that surrounds the first channel layer and the second channel layer. A source/drain feature disposed adjacent the first channel layer, second channel layer, and gate stack. The source/drain feature is disposed over first facets of the first channel layer and second facets of the second channel layer. The first facets and the second facets have a (111) crystallographic orientation. An inner spacer disposed between the gate stack and the source/drain feature and between the first channel layer and the second channel layer. A silicide feature is disposed over the source/drain feature where the silicide feature extends into the source/drain feature towards the substrate to a depth of the first channel layer.

公开(公告)号：US09318322B2

公开(公告)日：2016-04-19

申请号：US14541050

申请日：2014-11-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Zhiqiang Wu ,  Ken-Ichi Goto ,  Wen-Hsing Hsieh ,  Jon-Hsu Ho ,  Chih-Ching Wang ,  Ching-Fang Huang

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/36 ,  H01L21/02 ,  H01L29/66 ,  H01L29/10

CPC分类号： H01L21/02362 ,  H01L21/02123 ,  H01L21/02293 ,  H01L21/0234 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

摘要： System and method for controlling the channel thickness and preventing variations due to formation of small features. An embodiment comprises a fin raised above the substrate and a capping layer is formed over the fin. The channel carriers are repelled from the heavily doped fin and confined within the capping layer. This forms a thin-channel that allows greater electrostatic control of the gate.

摘要翻译： 用于控制通道厚度并防止由于形成小特征而引起的变化的系统和方法。 一个实施例包括在衬底上升起的翅片，并且在翅片上形成覆盖层。 通道载体从重掺杂的翅片排斥并限制在封盖层内。 这形成了允许对栅极进行更大静电控制的薄通道。

公开(公告)号：US11508807B2

公开(公告)日：2022-11-22

申请号：US17104666

申请日：2020-11-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Ching Wang ,  Wen-Hsing Hsieh ,  Jon-Hsu Ho ,  Wen-Yuan Chen ,  Chia-Ying Su ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/423 ,  H01L29/08

摘要： Embodiments relate to a semiconductor device structure including a first channel layer having a first surface and a second surface, a second channel layer having a first surface and a second surface, and the first and second channel layers are formed of a first material. The structure also includes a first dopant suppression layer in contact with the second surface of the first channel layer, and a second dopant suppression layer parallel to the first dopant suppression layer. The second dopant suppression layer is in contact with the first surface of the second channel layer, and the first and second dopant suppression layers each comprises carbon or fluorine. The structure further includes a gate dielectric layer in contact with the first and second dopant suppression layers and the first surface of the first channel layer, and a gate electrode layer disposed on the gate dielectric layer.

公开(公告)号：US20220336614A1

公开(公告)日：2022-10-20

申请号：US17231925

申请日：2021-04-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Ching Wang ,  Chung-I Yang ,  Jon-Hsu Ho ,  Wen-Hsing Hsieh ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC分类号： H01L29/45 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/285 ,  H01L21/306 ,  H01L21/764 ,  H01L29/66

摘要： Source/drain silicide that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a first channel layer disposed over a substrate, a second channel layer disposed over the first channel layer, and a gate stack that surrounds the first channel layer and the second channel layer. A source/drain feature disposed adjacent the first channel layer, second channel layer, and gate stack. The source/drain feature is disposed over first facets of the first channel layer and second facets of the second channel layer. The first facets and the second facets have a (111) crystallographic orientation. An inner spacer disposed between the gate stack and the source/drain feature and between the first channel layer and the second channel layer. A silicide feature is disposed over the source/drain feature where the silicide feature extends into the source/drain feature towards the substrate to a depth of the first channel layer.

公开(公告)号：US20140151761A1

公开(公告)日：2014-06-05

申请号：US13693685

申请日：2012-12-04

申请人： Taiwan Semiconductor Manufacturing Company, LTD.

发明人： Wen-Hsing Hsieh ,  Zhiqiang Wu ,  Ching-Fang Huang ,  Jon-Hsu Ho

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/66545 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/7853

摘要： A FinFET device and method for fabricating a FinFET device are disclosed. An exemplary method includes providing a substrate; forming a fin over the substrate; forming an isolation feature over substrate; forming a gate structure including a dummy gate over a portion of the fin, the gate structure traversing the fin, wherein the gate structure separates a source region and a drain region of the fin, a channel being defined in the portion of the fin between the source region and the drain region; and replacing the dummy gate of the gate structure with a metal gate, wherein during the replacing the dummy gate, a profile of the portion of the fin is modified. In an example, modifying the profile of the portion of the fin includes increasing a height of the portion of the fin and/or decreasing a width of the portion of the fin.

摘要翻译： 公开了一种用于制造FinFET器件的FinFET器件和方法。 一种示例性方法包括提供基底; 在基板上形成翅片; 在衬底上形成隔离特征; 在所述鳍片的一部分上形成包括虚拟栅极的栅极结构，所述栅极结构穿过所述鳍片，其中所述栅极结构分离所述鳍片的源极区域和漏极区域，在所述鳍片的所述部分中限定的沟道 源区和漏区; 并且用金属栅极替换栅极结构的虚拟栅极，其中在更换伪栅极期间改变鳍部分的轮廓。 在一个实例中，修改翅片部分的轮廓包括增加翅片部分的高度和/或减小翼片的该部分的宽度。

公开(公告)号：US12040381B2

公开(公告)日：2024-07-16

申请号：US18130296

申请日：2023-04-03

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Cheng-Yi Peng ,  Wen-Yuan Chen ,  Wen-Hsing Hsieh ,  Yi-Ju Hsu ,  Jon-Hsu Ho ,  Song-Bor Lee ,  Bor-Zen Tien

IPC分类号： H01L23/00 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

CPC分类号： H01L29/66545 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02203 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L27/0886

摘要： A method of manufacturing a semiconductor device, a plurality of fin structures are formed over a semiconductor substrate. The fin structures extend along a first direction and are arranged in a second direction crossing the first direction. A plurality of sacrificial gate structures extending in the second direction are formed over the fin structures. An interlayer dielectric layer is formed over the plurality of fin structures between adjacent sacrificial gate structures. The sacrificial gate structures are cut into a plurality of pieces of sacrificial gate structures by forming gate end spaces along the second direction. Gate separation plugs are formed by filling the gate end spaces with two or more dielectric materials. The two or more dielectric materials includes a first layer and a second layer formed on the first layer, and a dielectric constant of the second layer is smaller than a dielectric constant of the first layer.

公开(公告)号：US20220367612A1

公开(公告)日：2022-11-17

申请号：US17875221

申请日：2022-07-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Ching Wang ,  Wen-Hsing Hsieh ,  Jon-Hsu Ho ,  Wen-Yuan Chen ,  Chia-Ying Su ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/423 ,  H01L29/08

摘要： Embodiments relate to a semiconductor device structure including a first channel layer having a first surface and a second surface, a second channel layer having a first surface and a second surface, and the first and second channel layers are formed of a first material. The structure also includes a first dopant suppression layer in contact with the second surface of the first channel layer, and a second dopant suppression layer parallel to the first dopant suppression layer. The second dopant suppression layer is in contact with the first surface of the second channel layer, and the first and second dopant suppression layers each comprises carbon or fluorine. The structure further includes a gate dielectric layer in contact with the first and second dopant suppression layers and the first surface of the first channel layer, and a gate electrode layer disposed on the gate dielectric layer.