利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

12 条记录 (耗时 0.016 秒)

    MEMORY DEVICES INCLUDING TRANSISTORS ON MULTIPLE LAYERS
    2.
    发明公开
    MEMORY DEVICES INCLUDING TRANSISTORS ON MULTIPLE LAYERS 审中-公开

    公开(公告)号：US20230164970A1

    公开(公告)日：2023-05-25

    申请号：US17743233

    申请日：2022-05-12

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Ken-Ichi Goto ,  Cheng-Yi Wu

    IPC分类号： H01L27/11 ,  H01L29/786 ,  H01L23/528 ,  H01L29/66 ,  H01L21/8234

    CPC分类号： H01L27/1108 ,  H01L29/7869 ,  H01L29/78618 ,  H01L23/5283 ,  H01L29/66742 ,  H01L21/823431 ,  H01L21/823418

    摘要： A semiconductor device including a substrate, a first layer over the substrate, and a second layer over the first layer. The first layer including a first fin structure, a first gate structure that overlaps the first fin structure to form a first pass-gate transistor, and a second gate structure that is separate from the first gate structure and that overlaps the first fin structure to form a first pull-down transistor. The second layer including a third gate structure disposed over the second gate structure and connected to the second gate structure, a first semiconductor oxide structure disposed on the third gate structure, and a first drain/source region and a second drain/source region disposed on the first semiconductor oxide structure, wherein the third gate structure, the first semiconductor oxide structure, the first drain/source region, and the second drain/source region constitute a first pull-up transistor.

    Non-Uniform Channel Junction-Less Transistor
    6.
    发明申请
    Non-Uniform Channel Junction-Less Transistor 有权
    非均匀通道无结晶体管

    公开(公告)号：US20140024182A1

    公开(公告)日：2014-01-23

    申请号：US13941199

    申请日：2013-07-12

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Ken-Ichi Goto ,  Zhiqiang Wu

    IPC分类号： H01L29/66

    CPC分类号： H01L29/66803 ,  G01N33/6893 ,  H01L29/785 ,  H01L2029/7857

    摘要： The present disclosure discloses a method of forming a semiconductor layer on a substrate. The method includes patterning the semiconductor layer into a fin structure. The method includes forming a gate dielectric layer and a gate electrode layer over the fin structure. The method includes patterning the gate dielectric layer and the gate electrode layer to form a gate structure in a manner so that the gate structure wraps around a portion of the fin structure. The method includes performing a plurality of implantation processes to form source/drain regions in the fin structure. The plurality of implantation processes are carried out in a manner so that a doping profile across the fin structure is non-uniform, and a first region of the portion of the fin structure that is wrapped around by the gate structure has a lower doping concentration level than other regions of the fin structure.

    摘要翻译： 本公开公开了一种在衬底上形成半导体层的方法。 该方法包括将半导体层图案化成翅片结构。 该方法包括在鳍结构上形成栅介电层和栅电极层。 该方法包括以栅极结构缠绕翅片结构的一部分的方式构图栅极电介质层和栅极电极层以形成栅极结构。 该方法包括执行多个注入工艺以在散热片结构中形成源极/漏极区域。 多个注入工艺以这样一种方式进行，使得跨鳍片结构的掺杂分布不均匀，鳍结构部分被栅极结构缠绕的部分的第一区域具有较低的掺杂浓度水平 比其他地区的鳍结构。

    SPACER-DEFINED BACK-END TRANSISTOR AS MEMORY SELECTOR
    7.
    发明申请
    SPACER-DEFINED BACK-END TRANSISTOR AS MEMORY SELECTOR 有权

    公开(公告)号：US20220246678A1

    公开(公告)日：2022-08-04

    申请号：US17718481

    申请日：2022-04-12

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Ken-Ichi Goto ,  Chung-Te Lin ,  Mauricio Manfrini

    IPC分类号： H01L27/22 ,  H01L27/24

    摘要： The present disclosure, in some embodiments, relates to a memory device. In some embodiments, the memory device comprises a substrate and a lower interconnect metal layer disposed over the substrate. A selecting transistor is disposed over the lower interconnect metal layer. A memory cell is disposed over the selecting transistor and comprises a bottom electrode electrically connected to the selecting transistor, a data storage structure disposed over the bottom electrode, and a top electrode disposed over the data storage structure.