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公开(公告)号：US11798916B2
公开(公告)日：2023-10-24
申请号：US16048777
申请日：2018-07-30
发明人： Shu-Ting Tsai , Dun-Nian Yaung , Jen-Cheng Liu , Chun-Chieh Chuang , Chia-Chieh Lin , U-Ting Chen
IPC分类号： H01L23/48 , H01L25/065 , H01L25/00 , H01L21/768 , H01L23/00 , H01L23/532
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/481 , H01L24/92 , H01L25/50 , H01L21/76805 , H01L21/76831 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L24/80 , H01L24/82 , H01L2224/24145 , H01L2224/80896 , H01L2224/821 , H01L2224/8203 , H01L2224/82106 , H01L2224/9202 , H01L2224/9212 , H01L2225/06541 , H01L2924/0002 , H01L2224/8203 , H01L2224/821 , H01L2224/9212 , H01L2224/80001 , H01L2224/82
摘要： An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls and a bottom of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.
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2.发明授权公开(公告)号：US10304818B2
公开(公告)日：2019-05-28
申请号：US15836580
申请日：2017-12-08
发明人： Shu-Ting Tsai , Dun-Nian Yaung , Jen-Cheng Liu , Szu-Ying Chen , U-Ting Chen
IPC分类号： H01L21/768 , H01L25/00 , H01L23/48 , H01L25/065 , H01L23/00
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a first semiconductor chip including a first substrate and a first conductive feature formed over the first substrate, and a second semiconductor chip bonded to the first semiconductor chip. The second semiconductor chip includes a second substrate and a second conductive feature formed over the second substrate. A conductive plug is disposed through the first conductive feature and is coupled to the second conductive feature. The conductive plug includes a first portion disposed over the first conductive feature, the first portion having a first width, and a second portion disposed beneath or within the first conductive feature. The second portion has a second width. The first width is greater than the second width.
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3.发明授权公开(公告)号：US09748304B2
公开(公告)日：2017-08-29
申请号：US14133387
申请日：2013-12-18
发明人： U-Ting Chen , Shu-Ting Tsai , Szu-Ying Chen , Jeng-Shyan Lin , Dun-Nian Yaung , Jen-Cheng Liu
IPC分类号： H01L31/00 , H01L27/146 , H01L25/00 , H01L27/06 , H01L21/768 , H01L27/28 , H01L23/48 , H01L31/18
CPC分类号： H01L27/14645 , H01L21/76805 , H01L21/76807 , H01L21/76898 , H01L23/481 , H01L25/00 , H01L25/50 , H01L27/0688 , H01L27/14621 , H01L27/14636 , H01L27/1464 , H01L27/14685 , H01L27/14687 , H01L27/14689 , H01L27/281 , H01L31/1876 , H01L2224/08145 , H01L2224/80894 , H01L2224/80895 , H01L2224/80896 , H01L2224/9202 , H01L2224/9212 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2224/80 , H01L2224/8203 , H01L2224/821 , H01L2224/80001 , H01L2224/82
摘要： Image sensor devices, methods of manufacture thereof, and semiconductor device manufacturing methods are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes bonding a first semiconductor wafer to a second semiconductor wafer, the first semiconductor wafer comprising a substrate and an interconnect structure coupled to the substrate. The method includes removing a portion of the substrate from the first semiconductor wafer to expose a portion of the interconnect structure.
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公开(公告)号：US10269843B2
公开(公告)日：2019-04-23
申请号：US15905033
申请日：2018-02-26
发明人： Hung-Wen Hsu , Jiech-Fun Lu , Yeur-Luen Tu , U-Ting Chen , Shu-Ting Tsai , Hsiu-Yu Cheng
IPC分类号： H01L27/146
摘要： A backside illumination (BSI) image sensor and a method of forming the same are provided. A method includes forming a plurality of photosensitive pixels in a substrate, the substrate having a first surface and a second surface, the second surface being opposite the first surface, the substrate having one or more active devices on the first surface. A first portion of the second surface is protected. A second portion of the second surface is patterned to form recesses in the substrate. An anti-reflective layer is formed on sidewalls of the recesses. A metal grid is formed over the second portion of the second surface, the anti-reflective layer being interposed between the substrate and the metal grid.
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公开(公告)号：US20160351546A1
公开(公告)日：2016-12-01
申请号：US15231419
申请日：2016-08-08
发明人： Shu-Ting Tsai , Dun-Nian Yaung , Jen-Cheng Liu , U-Ting Chen , Shih-Pei Chou
IPC分类号： H01L25/065 , H01L21/311 , H01L23/00 , H01L21/3105 , H01L23/48 , H01L25/00 , H01L21/768
CPC分类号： H01L25/0657 , H01L21/31051 , H01L21/31111 , H01L21/76805 , H01L21/76831 , H01L21/76832 , H01L21/76877 , H01L21/76898 , H01L23/481 , H01L24/24 , H01L24/80 , H01L24/82 , H01L24/91 , H01L25/50 , H01L2224/24051 , H01L2224/24146 , H01L2224/80895 , H01L2224/80896 , H01L2224/82031 , H01L2224/821 , H01L2224/92 , H01L2224/9202 , H01L2224/9212 , H01L2224/94 , H01L2225/06541 , H01L2924/12036 , H01L2924/00 , H01L2224/80001 , H01L2224/82 , H01L2224/8203
摘要： An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls of the first opening. One or more etch processes form one or more spacer-shaped structures along sidewalls of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.
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公开(公告)号：US20150179613A1
公开(公告)日：2015-06-25
申请号：US14135153
申请日：2013-12-19
发明人： Shu-Ting Tsai , Dun-Nian Yaung , Jen-Cheng Liu , Chun-Chieh Chuang , Chia-Chieh Lin , U-Ting Chen
IPC分类号： H01L25/065 , H01L23/48 , H01L25/00 , H01L21/768 , H01L23/528 , H01L23/532
CPC分类号： H01L25/0657 , H01L21/76805 , H01L21/76831 , H01L21/76898 , H01L23/481 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L24/80 , H01L24/82 , H01L24/92 , H01L25/50 , H01L2224/24145 , H01L2224/80896 , H01L2224/82106 , H01L2224/9202 , H01L2224/9212 , H01L2225/06541 , H01L2924/0002 , H01L2924/00 , H05K3/467 , H01L2224/8203 , H01L2224/821 , H01L2224/80001 , H01L2224/82
摘要： An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls and a bottom of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.
摘要翻译： 提供了互连装置和形成互连装置的方法。 两个集成电路结合在一起。 通过一个基板形成第一开口。 沿着第一开口的侧壁和底部形成多层电介质膜。 形成从第一开口延伸到集成电路中的焊盘的第二开口。 形成电介质衬垫，并且用导电材料填充开口以形成导电插塞。
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公开(公告)号：US20150179612A1
公开(公告)日：2015-06-25
申请号：US14135103
申请日：2013-12-19
发明人： Shu-Ting Tsai , Dun-Nian Yaung , Jen-Cheng Liu , U-Ting Chen , Shih Pei Chou
IPC分类号： H01L25/065 , H01L23/00 , H01L25/00
CPC分类号： H01L25/0657 , H01L21/31051 , H01L21/31111 , H01L21/76805 , H01L21/76831 , H01L21/76832 , H01L21/76877 , H01L21/76898 , H01L23/481 , H01L24/24 , H01L24/80 , H01L24/82 , H01L24/91 , H01L25/50 , H01L2224/24051 , H01L2224/24146 , H01L2224/80895 , H01L2224/80896 , H01L2224/82031 , H01L2224/821 , H01L2224/92 , H01L2224/9202 , H01L2224/9212 , H01L2224/94 , H01L2225/06541 , H01L2924/12036 , H01L2924/00 , H01L2224/80001 , H01L2224/82 , H01L2224/8203
摘要： An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls of the first opening. One or more etch processes form one or more spacer-shaped structures along sidewalls of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.
摘要翻译： 提供了互连装置和形成互连装置的方法。 两个集成电路结合在一起。 通过一个基板形成第一开口。 沿第一开口的侧壁形成多层电介质膜。 一个或多个蚀刻工艺沿着第一开口的侧壁形成一个或多个间隔物结构。 形成从第一开口延伸到集成电路中的焊盘的第二开口。 形成电介质衬垫，并且用导电材料填充开口以形成导电插塞。
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公开(公告)号：US20140264862A1
公开(公告)日：2014-09-18
申请号：US13839860
申请日：2013-03-15
发明人： Shu-Ting Tsai , Dun-Nian Yaung , Cheng-Jong Wang , Jen-Cheng Liu , Feng-Chi Hung , Tzu-Hsuan Hsu , U-Ting Chen , Jeng-Shyan Lin , Shuang-Ji Tsai
IPC分类号： H01L25/00
CPC分类号： H01L27/14645 , H01L21/76805 , H01L21/76807 , H01L21/76898 , H01L23/481 , H01L25/00 , H01L25/50 , H01L27/0688 , H01L27/14621 , H01L27/14636 , H01L27/1464 , H01L27/14685 , H01L27/14687 , H01L27/14689 , H01L27/281 , H01L31/1876 , H01L2224/08145 , H01L2224/80894 , H01L2224/80895 , H01L2224/80896 , H01L2224/9202 , H01L2224/9212 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2224/80 , H01L2224/8203 , H01L2224/821 , H01L2224/80001 , H01L2224/82
摘要： A semiconductor device comprises a first semiconductor chip including a first substrate and a plurality of first metal lines formed over the first substrate and a second semiconductor chip bonded on the first semiconductor chip, wherein the second semiconductor chip comprises a second substrate and a plurality of second metal lines formed over the second substrate. The semiconductor device further comprises a conductive plug coupled between the first metal lines and the second metal lines, wherein the conductive plug comprises a first portion formed over a first side of a hard mask layer, wherein the first portion is of a first width and a second portion formed over a second side of the hard mask layer, wherein the second portion is of a second width greater than or equal to the first width.
摘要翻译： 半导体器件包括：第一半导体芯片，包括第一衬底和形成在第一衬底上的多个第一金属线;以及第二半导体芯片，其接合在第一半导体芯片上，其中第二半导体芯片包括第二衬底和多个第二衬底 形成在第二基板上的金属线。 所述半导体器件还包括耦合在所述第一金属线和所述第二金属线之间的导电插塞，其中所述导电插塞包括形成在硬掩模层的第一侧上的第一部分，其中所述第一部分具有第一宽度和 第二部分形成在硬掩模层的第二侧上，其中第二部分具有大于或等于第一宽度的第二宽度。
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公开(公告)号：US11916091B2
公开(公告)日：2024-02-27
申请号：US17231223
申请日：2021-04-15
发明人： Hung-Wen Hsu , Jiech-Fun Lu , Yeur-Luen Tu , U-Ting Chen , Shu-Ting Tsai , Hsiu-Yu Cheng
IPC分类号： H01L27/14 , H01L27/146
CPC分类号： H01L27/1462 , H01L27/14623 , H01L27/1464 , H01L27/14685 , H01L27/14689
摘要： A backside illumination (BSI) image sensor and a method of forming the same are provided. A device includes a substrate and a plurality of photosensitive regions in the substrate. The substrate has a first side and a second side opposite to the first side. The device further includes an interconnect structure on the first side of the substrate, and a plurality of recesses on the second side of the substrate. The plurality of recesses extend into a semiconductor material of the substrate.
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公开(公告)号：US10510729B2
公开(公告)日：2019-12-17
申请号：US16208660
申请日：2018-12-04
发明人： Shu-Ting Tsai , Dun-Nian Yaung , Jen-Cheng Liu , U-Ting Chen , Shih Pei Chou
IPC分类号： H01L21/768 , H01L25/065 , H01L25/00 , H01L23/00 , H01L23/48 , H01L21/3105 , H01L21/311
摘要： An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls of the first opening. One or more etch processes form one or more spacer-shaped structures along sidewalls of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.
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