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公开(公告)号：US12300670B2
公开(公告)日：2025-05-13
申请号：US18355524
申请日：2023-07-20
Inventor： Sin-Yao Huang , Chun-Chieh Chuang , Ching-Chun Wang , Sheng-Chau Chen , Dun-Nian Yaung , Feng-Chi Hung , Yung-Lung Lin
IPC: H01L25/065 , H01L23/00 , H01L23/498 , H01L25/00 , H10F39/00 , H01L23/52
Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first integrated chip (IC) tier and a second IC tier. The second IC tier comprises a second plurality of conductors within a second insulating structure disposed on the second semiconductor body. A conductive pad is electrically coupled to the second plurality of conductors and has a conductive surface available to a side of the second semiconductor body facing away from the first semiconductor body. The IC first tier contacts the second IC tier along a bonding interface including one or more conductive regions and one or more insulating regions. The one or more conductive regions laterally outside of a bottom surface of the conductive pad.
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公开(公告)号：US20250133856A1
公开(公告)日：2025-04-24
申请号：US18490246
申请日：2023-10-19
Inventor： Shen-Hui Hong , Chun-Chieh Chuang , Feng-Chi Hung , Jen-Cheng Liu
IPC: H01L27/146 , H01L23/00
Abstract: Various embodiments of the present disclosure are directed towards an image sensor including a first integrated circuit (IC) die stacked with a second IC die. The first IC die includes a plurality of photodetectors disposed within a first substrate. The second IC die includes a plurality of pixel transistors and a semiconductor capacitor disposed on a second substrate. The semiconductor capacitor includes a first capacitor electrode, a capacitor dielectric layer, and a doped capacitor region. The first capacitor electrode overlies the second substrate and comprises a protrusion disposed in the second substrate. The capacitor dielectric layer is disposed between the first capacitor electrode and the second substrate. The doped capacitor region is disposed within the second substrate and underlies the first capacitor electrode. The plurality of photodetectors, the plurality of pixel transistors, and the semiconductor capacitor define a pixel.
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公开(公告)号：US20230361085A1
公开(公告)日：2023-11-09
申请号：US18355524
申请日：2023-07-20
Inventor： Sin-Yao Huang , Chun-Chieh Chuang , Ching-Chun Wang , Sheng-Chau Chen , Dun-Nian Yaung , Feng-Chi Hung , Yung-Lung Lin
IPC: H01L25/065 , H01L23/498 , H01L25/00 , H01L27/146 , H01L23/00
CPC classification number: H01L25/0657 , H01L23/49838 , H01L24/00 , H01L25/50 , H01L27/14634 , H01L27/14636 , H01L23/52
Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first integrated chip (IC) tier and a second IC tier. The second IC tier comprises a second plurality of conductors within a second insulating structure disposed on the second semiconductor body. A conductive pad is electrically coupled to the second plurality of conductors and has a conductive surface available to a side of the second semiconductor body facing away from the first semiconductor body. The IC first tier contacts the second IC tier along a bonding interface including one or more conductive regions and one or more insulating regions. The one or more conductive regions laterally outside of a bottom surface of the conductive pad.
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公开(公告)号：US10682523B2
公开(公告)日：2020-06-16
申请号：US16154154
申请日：2018-10-08
Inventor： Shu-Ting Tsai , Jeng-Shyan Lin , Chun-Chieh Chuang , Dun-Nian Yaung , Jen-Cheng Liu , Feng-Chi Hung
IPC: H01L23/48 , H01L23/52 , H01L29/40 , A61N1/39 , H01L25/00 , H01L27/06 , H01L27/146 , H01L21/768 , H01L23/532
Abstract: A semiconductor device comprises a first chip bonded on a second chip. The first chip comprises a first substrate and first interconnection components formed in first IMD layers. The second chip comprises a second substrate and second interconnection components formed in second IMD layers. The device further comprises a first conductive plug formed within the first substrate and the first IMD layers, wherein the first conductive plug is coupled to a first interconnection component and a second conductive plug formed through the first substrate and the first IMD layers and formed partially through the second IMD layers, wherein the second conductive plug is coupled to a second interconnection component.
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公开(公告)号：US10535697B2
公开(公告)日：2020-01-14
申请号：US15803913
申请日：2017-11-06
Inventor： Min-Feng Kao , Dun-Nian Yaung , Jen-Cheng Liu , Chun-Chieh Chuang , Feng-Chi Hung , Shuang-Ji Tsai , Jen-Shyan Lin , Shu-Ting Tsai , Wen-I Hsu
IPC: H01L27/14 , H01L27/146 , H01L31/02
Abstract: An image sensor structure that includes a first semiconductor substrate having a plurality of imaging sensors; a first interconnect structure formed on the first semiconductor substrate; a second semiconductor substrate having a logic circuit; a second interconnect structure formed on the second semiconductor substrate, wherein the first and the second semiconductor substrates are bonded together in a configuration that the first and second interconnect structures are sandwiched between the first and second semiconductor substrates; and a backside deep contact (BDCT) feature extended from the first interconnect structure to the second interconnect structure, thereby electrically coupling the logic circuit to the image sensors.
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Patent Agency Ranking
公开(公告)号：US20190046806A1
公开(公告)日：2019-02-14
申请号：US16154154
申请日：2018-10-08
Inventor： Shu-Ting Tsai , Jeng-Shyan Lin , Chun-Chieh Chuang , Dun-Nian Yaung , Jen-Cheng Liu , Feng-Chi Hung
IPC: A61N1/39 , H01L21/768 , H01L23/48 , H01L23/532 , H01L25/00 , H01L27/06 , H01L27/146
Abstract: A semiconductor device comprises a first chip bonded on a second chip. The first chip comprises a first substrate and first interconnection components formed in first IMD layers. The second chip comprises a second substrate and second interconnection components formed in second IMD layers. The device further comprises a first conductive plug formed within the first substrate and the first IMD layers, wherein the first conductive plug is coupled to a first interconnection component and a second conductive plug formed through the first substrate and the first IMD layers and formed partially through the second IMD layers, wherein the second conductive plug is coupled to a second interconnection component.
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公开(公告)号：US20160336367A1
公开(公告)日：2016-11-17
申请号：US15218266
申请日：2016-07-25
Inventor： Chun-Chieh Chuang , Dun-Nian Yaung , Jen-Cheng Liu , Wen-De Wang , Keng-Yu Chou , Shuang-Ji Tsai , Min-Feng Kao
IPC: H01L27/146
CPC classification number: H01L27/14623 , H01L27/1462 , H01L27/14621 , H01L27/1464 , H01L27/14645 , H01L27/14685 , H01L27/14689 , H01L31/02161 , H01L31/1868 , Y02E10/50 , Y02P70/521
Abstract: A back side image sensor and method of manufacture are provided. In an embodiment a bottom anti-reflective coating is formed over a substrate, and a metal shield layer is formed over the bottom anti-reflective coating. The metal shield layer is patterned to form a grid pattern over a sensor array region of the substrate, and a first dielectric layer and a second dielectric layer are formed to at least partially fill in openings within the grid pattern.
Abstract translation: 提供背面图像传感器及其制造方法。 在一个实施例中，底部抗反射涂层形成在衬底上，并且金属屏蔽层形成在底部抗反射涂层上。 金属屏蔽层被图案化以在衬底的传感器阵列区域上形成网格图案，并且形成第一电介质层和第二电介质层以至少部分填充网格图案内的开口。
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公开(公告)号：US09401380B2
公开(公告)日：2016-07-26
申请号：US14280379
申请日：2014-05-16
Inventor： Chun-Chieh Chuang , Dun-Nian Yaung , Jen-Cheng Liu , Wen-De Wang , Keng-Yu Chou , Shuang-Ji Tsai , Min-Feng Kao
IPC: H01L27/146 , H01L31/0216 , H01L31/18
CPC classification number: H01L27/14623 , H01L27/1462 , H01L27/14621 , H01L27/1464 , H01L27/14645 , H01L27/14685 , H01L27/14689 , H01L31/02161 , H01L31/1868 , Y02E10/50 , Y02P70/521
Abstract: A back side image sensor and method of manufacture are provided. In an embodiment a bottom anti-reflective coating is formed over a substrate, and a metal shield layer is formed over the bottom anti-reflective coating. The metal shield layer is patterned to form a grid pattern over a sensor array region of the substrate, and a first dielectric layer and a second dielectric layer are formed to at least partially fill in openings within the grid pattern.
Abstract translation: 提供背面图像传感器及其制造方法。 在一个实施例中，底部抗反射涂层形成在衬底上，并且金属屏蔽层形成在底部抗反射涂层上。 金属屏蔽层被图案化以在衬底的传感器阵列区域上形成网格图案，并且形成第一电介质层和第二电介质层以至少部分填充网格图案内的开口。
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9.发明授权Semiconductor devices, methods of manufacturing thereof, and image sensor devices 有权半导体器件，其制造方法和图像传感器器件公开(公告)号：US09391114B2
公开(公告)日：2016-07-12
申请号：US14326268
申请日：2014-07-08
Inventor： Chun-Chieh Chuang , Dun-Nian Yaung , Feng-Chi Hung , Min-Feng Kao , Jeng-Shyan Lin , Chun-Ming Su , Ching-Chun Wang
IPC: H01L31/00 , H01L27/146 , H01L23/48 , H01L21/48 , H01L23/58 , H01L23/31 , H01L23/522
CPC classification number: H01L27/14636 , H01L21/486 , H01L23/3114 , H01L23/481 , H01L23/522 , H01L23/585 , H01L27/14634 , H01L27/1464 , H01L27/14687 , H01L27/1469 , H01L2224/08145 , H01L2924/0002 , H01L2924/00
Abstract: Semiconductor devices, methods of manufacturing thereof, and image sensor devices are disclosed. In some embodiments, a semiconductor device includes a semiconductor chip comprising an array region, a periphery region, and a through-via disposed therein. A guard structure is disposed in the semiconductor chip between the array region and the through-via or between the through-via and a portion of the periphery region. A portion of the guard structure is disposed within a substrate of the semiconductor chip.
Abstract translation: 公开了半导体器件，其制造方法和图像传感器器件。 在一些实施例中，半导体器件包括包括阵列区域，外围区域和设置在其中的通孔的半导体芯片。 保护结构设置在半导体芯片之间的阵列区域和通孔之间，或贯穿通孔与外围区域的一部分之间。 保护结构的一部分设置在半导体芯片的基板内。
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公开(公告)号：US20160141325A1
公开(公告)日：2016-05-19
申请号：US15005803
申请日：2016-01-25
Inventor： Min-Feng Kao , Dun-Nian Yaung , Jen-Cheng Liu , Feng-Chi Hung , Chun-Chieh Chuang , Shuang-Ji Tsai , Jeng-Shyan Lin
IPC: H01L27/146 , H01L31/18
CPC classification number: H01L27/14636 , H01L27/14601 , H01L27/14612 , H01L27/14632 , H01L27/14634 , H01L27/1464 , H01L31/186
Abstract: A method and apparatus for a low resistance image sensor contact, the apparatus comprising a photosensor disposed in a substrate, a first ground well disposed in a first region of the substrate, the first ground well having a resistance lower than the substrate, and a ground line disposed in a region adjacent to the first ground well. The first ground well is configured to provide a low resistance path to the ground line from the substrate for excess free carriers in the first region of the substrate. The apparatus may optionally comprise a second ground well having a lower resistance than the first ground well and disposed between the first ground well and the ground line, and may further optionally comprise a third ground well having a lower resistance than the second ground well and disposed between the second ground well and the ground line.
Abstract translation: 一种用于低电阻图像传感器接触的方法和装置，所述装置包括设置在基板中的光电传感器，设置在基板的第一区域中的第一接地阱，具有比基板低的电阻的第一接地阱和地面 设置在与第一接地井相邻的区域中。 第一接地阱被配置为在衬底的第一区域中为过剩自由载流子提供从衬底到接地线的低电阻路径。 该设备可以可选地包括具有比第一接地井更低的电阻并且设置在第一接地井和接地线之间的第二接地井，并且还可以进一步可选地包括具有比第二接地井更低的电阻的第三地下井，并且设置 在第二地面井和地面线之间。
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