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公开(公告)号:US20220384190A1
公开(公告)日:2022-12-01
申请号:US17818450
申请日:2022-08-09
Inventor: Chih-Ming LAI , Shih-Ming CHANG , Wei-Liang LIN , Chin-Yuan TSENG , Ru-Gun LIU
IPC: H01L21/033 , H01L21/311
Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first spacer over a substrate. The method includes partially removing the first spacer to form a gap dividing the first spacer into a first part and a second part. The method includes forming a filling layer covering a first top surface and a first sidewall of the first spacer. The filling layer and the first spacer together form a strip structure. The method includes forming a second spacer over a second sidewall of the strip structure. The method includes forming a third spacer over a third sidewall of the second spacer. The third spacer is narrower than the second spacer.
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公开(公告)号:US20190019797A1
公开(公告)日:2019-01-17
申请号:US16126875
申请日:2018-09-10
Inventor: Chih-Liang CHEN , Chih-Ming LAI , Charles Chew-Yuen YOUNG , Chin-Yuan TSENG , Jiann-Tyng TZENG , Kam-Tou SIO , Ru-Gun LIU , Wei-Liang LIN , L. C. CHOU
IPC: H01L27/11 , H01L27/088 , H01L21/8234 , H01L21/308 , H01L21/311
CPC classification number: H01L27/1104 , H01L21/3083 , H01L21/3086 , H01L21/31144 , H01L21/823431 , H01L27/0886 , H01L29/66795 , H01L29/7851
Abstract: A semiconductor device including multiple fins. At least a first set of fins among the multiple fins is substantially parallel. At least a second set of fins among the multiple fins is substantially collinear. For any given first and second fins of the multiple fins having corresponding first and second fin-thicknesses, the second fin-thickness is less than plus or minus about 50% of the first fin-thickness.
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公开(公告)号:US20220157605A1
公开(公告)日:2022-05-19
申请号:US17589315
申请日:2022-01-31
Inventor: Shih-Chun HUANG , Chiu-Hsiang CHEN , Ya-Wen YEH , Yu-Tien SHEN , Po-Chin CHANG , Chien-Wen LAI , Wei-Liang LIN , Ya Hui CHANG , Yung-Sung YEN , Li-Te LIN , Pinyen LIN , Ru-Gun LIU , Chin-Hsiang LIN
IPC: H01L21/033 , H01L21/027 , H01L21/311 , H01L21/02 , H01L21/265
Abstract: A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.
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公开(公告)号:US20210375639A1
公开(公告)日:2021-12-02
申请号:US17403850
申请日:2021-08-16
Inventor: Ya-Wen YEH , Yu-Tien SHEN , Shih-Chun HUANG , Po-Chin CHANG , Wei-Liang LIN , Yung-Sung YEN , Wei-Hao WU , Li-Te LIN , Pinyen LIN , Ru-Gun LIU
IPC: H01L21/3213 , H01L21/66
Abstract: In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.
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公开(公告)号:US20200335507A1
公开(公告)日:2020-10-22
申请号:US16918798
申请日:2020-07-01
Inventor: Chih-Liang CHEN , Chih-Ming LAI , Charles Chew-Yuen YOUNG , Chin-Yuan TSENG , Jiann-Tyng TZENG , Kam-Tou SIO , Ru-Gun LIU , Wei-Liang LIN , L. C. CHOU
IPC: H01L27/11 , H01L21/308 , H01L27/088 , H01L29/66 , H01L29/78 , H01L21/8234
Abstract: A semiconductor device including fins arranged so that: in a situation in which any given first one of the fins (first given fin) is immediately adjacent any given second one of the fins (second given fin), and subject to fabrication tolerance, there is a minimum gap, Gmin, between the first and second given fins; and the first and second given fins a minimum pitch, Pmin, that falls in a range as follows: (Gmin+(≈90%)*T1)≤Pmin≤(Gmin+(≈110%)*T1).
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公开(公告)号:US20230247817A1
公开(公告)日:2023-08-03
申请号:US18190670
申请日:2023-03-27
Inventor: Chih-Liang CHEN , Chih-Ming LAI , Charles Chew-Yuen YOUNG , Chin-Yuan TSENG , Jiann-Tyng TZENG , Kam-Tou SIO , Ru-Gun LIU , Wei-Liang LIN , L. C. CHOU
IPC: H10B10/00 , H01L21/8234 , H01L27/088 , H01L21/308 , H01L29/78 , H01L29/66
CPC classification number: H10B10/12 , H01L21/823431 , H01L27/0886 , H01L21/3083 , H01L21/3086 , H01L29/7851 , H01L29/66795 , H01L21/31144
Abstract: A method (of manufacturing fins for a semiconductor device) includes: forming semiconductor fins including ones thereof having a first cap with a first etch sensitivity (first capped fins) and second ones thereof having a second cap with a second etch sensitivity (second capped fins), the first and second etch sensitivities being different; and eliminating selected ones of the first capped fins and selected ones of the second capped fins.
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公开(公告)号:US20220367201A1
公开(公告)日:2022-11-17
申请号:US17873113
申请日:2022-07-25
Inventor: Chin-Yuan TSENG , Yu-Tien SHEN , Wei-Liang LIN , Chih-Ming LAI , Kuo-Cheng CHING , Shi-Ning JU , Li-Te LIN , Ru-Gun LIU
IPC: H01L21/311 , H01L21/32 , H01L23/528 , H01L21/3213
Abstract: A method of reducing corner rounding during patterning of a substrate to form a prescribed pattern comprising a corner includes dividing the pattern into a first pattern and a second pattern, the first pattern forming a first edge of the corner and the second pattern forming a second edge of the corner. At least a portion of the second pattern overlaps the first pattern such that the first edge intersects with the second edge to form a corner of the prescribed pattern. The method further includes forming the first pattern in a first mask layer disposed on a substrate to expose the substrate and forming the second pattern in the first mask layer to expose the substrate. The substrate exposed through the first mask layer is then etched to obtain the pattern.
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公开(公告)号:US20240387247A1
公开(公告)日:2024-11-21
申请号:US18787501
申请日:2024-07-29
Inventor: Ru-Gun LIU , Chin-Hsiang LIN , Chih-Ming LAI , Wei-Liang LIN , Yung-Sung YEN
IPC: H01L21/768 , H01L27/12
Abstract: In accordance with an aspect of the present disclosure, in a pattern forming method for a semiconductor device, a first opening is formed in an underlying layer disposed over a substrate. The first opening is expanded in a first axis by directional etching to form a first groove in the underlying layer. A resist pattern is formed over the underlying layer. The resist pattern includes a second opening only partially overlapping the first groove. The underlying layer is patterned by using the resist pattern as an etching mask to form a second groove.
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公开(公告)号:US20220285168A1
公开(公告)日:2022-09-08
申请号:US17751361
申请日:2022-05-23
Inventor: Ru-Gun LIU , Chih-Ming LAI , Wei-Liang LIN , Yung-Sung YEN , Ken-Hsien HSIEH , Chin-Hsiang LIN
IPC: H01L21/311 , H01L21/027 , H01L21/768
Abstract: In a method of forming a groove pattern extending in a first axis in an underlying layer over a semiconductor substrate, a first opening is formed in the underlying layer, and the first opening is extended in the first axis by directional etching to form the groove pattern.
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公开(公告)号:US20220108990A1
公开(公告)日:2022-04-07
申请号:US17552433
申请日:2021-12-16
Inventor: Chih-Liang CHEN , Chih-Ming LAI , Charles Chew-Yuen YOUNG , Chin-Yuan TSENG , Jiann-Tyng TZENG , Kam-Tou SIO , Ru-Gun LIU , Wei-Liang LIN , L. C. CHOU
IPC: H01L27/11 , H01L21/8234 , H01L27/088 , H01L21/308 , H01L29/78 , H01L29/66
Abstract: In an embodiment, a method (of manufacturing fins for a semiconductor device) includes: forming a first layer (on a semiconductor substrate) that has first spacers and etch stop layer (ESL) portions which are interspersed; forming second spacers on central regions of the first spacers and the ESL portions; removing exposed regions of the first spacers and the ESL portions and corresponding underlying portions of the semiconductor substrate; removing the second spacers resulting in corresponding first capped semiconductor fins and second capped semiconductor fins that are organized into first and second sets; each member of the first set having a first cap with a first etch sensitivity; and each member of the second set having a second cap with a different second etch sensitivity; and eliminating selected ones of the first capped semiconductor fins and selected ones of the second capped semiconductor fins.
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