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公开(公告)号:US20240290854A1
公开(公告)日:2024-08-29
申请号:US18656033
申请日:2024-05-06
发明人: Tze-Chung LIN , Han-Yu LIN , Pinyen LIN , Fang-Wei LEE , Li-Te LIN
IPC分类号: H01L29/417 , H01L21/3065 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/786
CPC分类号: H01L29/41775 , H01L21/3065 , H01L29/0665 , H01L29/42392 , H01L29/66553 , H01L29/78696
摘要: The present disclosure describes a method includes forming a fin structure including a fin bottom portion and a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer and a second semiconductor layer, in which the first semiconductor layer includes germanium. The method further includes etching the fin structure to form an opening, delivering a primary etchant and a germanium-containing gas to the fin structure through the opening, and etching a portion of the second semiconductor layer in the opening with the primary etchant and the germanium-containing gas.
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公开(公告)号:US20240234549A1
公开(公告)日:2024-07-11
申请号:US18616449
申请日:2024-03-26
发明人: Han-Yu LIN , Chansyun David YANG , Fang-Wei LEE , Tze-Chung LIN , Li-Te LIN , Pinyen LIN
IPC分类号: H01L29/66 , H01L21/02 , H01L21/311 , H01L21/321 , H01L21/768 , H01L21/8234 , H01L29/06 , H01L29/165 , H01L29/423 , H01L29/775 , H01L29/78 , H01L29/786
CPC分类号: H01L29/6681 , H01L21/0214 , H01L21/02167 , H01L21/02532 , H01L21/02603 , H01L21/31116 , H01L21/32105 , H01L21/3211 , H01L21/7682 , H01L21/76837 , H01L21/823412 , H01L21/823418 , H01L21/823468 , H01L29/0673 , H01L29/165 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/66553 , H01L29/775 , H01L29/785 , H01L29/78696
摘要: A semiconductor device structure is provided. The semiconductor device structure includes forming semiconductor device structure includes a gate stack wrapping around a plurality of nanowire structures. The gate stack includes a first portion above the plurality of nanowire structures and second portions between the nanowire structures. The semiconductor device structure further includes a gate spacer layer along a sidewall of the first portion of the gate stack, and a plurality of inner spacer layers along sidewalls of the second portions of the gate stack. The gate spacer layer has a first carbon concentration, the inner spacer layers have a second carbon concentration, and the second carbon concentration is lower than the first carbon concentration.
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公开(公告)号:US20230018022A1
公开(公告)日:2023-01-19
申请号:US17377601
申请日:2021-07-16
发明人: Yu-Rung HSU , Li-Te LIN , Pinyen LIN
IPC分类号: H01J37/32 , H01L21/3065 , H01L21/311
摘要: A processing apparatus is provided. The processing apparatus includes a chamber and a carrier that is positioned in the chamber for holding a substrate. The processing apparatus further includes a gas inlet connected to the chamber. The gas inlet is configured to supply a process gas into the chamber. The processing apparatus also includes a coil module positioned around the chamber and configured to transfer the process gas into plasma. In addition, the processing apparatus includes a filter disposed in the chamber. The coil module is configured to change a position of the plasma between a first position and a second position, the first position is located between the gas inlet and the filter, and the second position is located between the filter and the carrier.
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公开(公告)号:US20220367201A1
公开(公告)日:2022-11-17
申请号:US17873113
申请日:2022-07-25
发明人: Chin-Yuan TSENG , Yu-Tien SHEN , Wei-Liang LIN , Chih-Ming LAI , Kuo-Cheng CHING , Shi-Ning JU , Li-Te LIN , Ru-Gun LIU
IPC分类号: H01L21/311 , H01L21/32 , H01L23/528 , H01L21/3213
摘要: A method of reducing corner rounding during patterning of a substrate to form a prescribed pattern comprising a corner includes dividing the pattern into a first pattern and a second pattern, the first pattern forming a first edge of the corner and the second pattern forming a second edge of the corner. At least a portion of the second pattern overlaps the first pattern such that the first edge intersects with the second edge to form a corner of the prescribed pattern. The method further includes forming the first pattern in a first mask layer disposed on a substrate to expose the substrate and forming the second pattern in the first mask layer to expose the substrate. The substrate exposed through the first mask layer is then etched to obtain the pattern.
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公开(公告)号:US20220336635A1
公开(公告)日:2022-10-20
申请号:US17854615
申请日:2022-06-30
发明人: Tze-Chung LIN , Han-Yu LIN , Li-Te LIN , Pinyen LIN
IPC分类号: H01L29/66 , H01L21/8234 , H01L29/78 , H01L29/423
摘要: A method for forming a semiconductor device structure is provided. The method includes forming first semiconductor layers and second semiconductor layers on a substrate, and the first semiconductor layers and the second semiconductor layers are alternately stacked. The method includes forming a dummy gate structure over the first semiconductor layers and the second semiconductor layers, and removing a portion of the first semiconductor layers and second semiconductor layers to form a S/D trench. The method also includes removing the second semiconductor layers to form a recess connected to the S/D trench. The method includes forming a dummy dielectric layer in the recess after the dummy gate structure is formed, and the dummy dielectric layer is exposed by the S/D trench. The method includes removing a portion of the dummy dielectric layer to form a cavity and forming an inner spacer layer in the cavity.
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公开(公告)号:US20240363721A1
公开(公告)日:2024-10-31
申请号:US18771578
申请日:2024-07-12
发明人: Po-Chin CHANG , Ming-Huan TSAI , Li-Te LIN , Pinyen LIN
IPC分类号: H01L29/49 , H01L21/8234 , H01L29/08 , H01L29/40 , H01L29/417 , H01L29/66 , H01L29/78
CPC分类号: H01L29/4983 , H01L21/823431 , H01L21/823475 , H01L29/0847 , H01L29/401 , H01L29/41791 , H01L29/66795 , H01L29/7851
摘要: A semiconductor device and methods of fabricating the same are disclosed. The method can include forming a fin structure on a substrate, forming a source/drain (S/D) region on the fin structure, forming a gate structure on the fin structure adjacent to the S/D region, and forming a capping structure on the gate structure. The forming the capping structure includes forming a conductive cap on the gate structure, forming a cap liner on the conductive cap, and forming a carbon-based cap on the cap liner. The method further includes forming a first contact structure on the S/D region, forming an insulating cap on the first contact structure, and forming a second contact structure on the conductive cap.
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公开(公告)号:US20230268386A1
公开(公告)日:2023-08-24
申请号:US17678481
申请日:2022-02-23
发明人: Han-Yu LIN , Che-Chi SHIH , Szu-Hua CHEN , Kuan-Da HUANG , Cheng-Ming LIN , Tze-Chung LIN , Li-Te LIN , Wei-Yen WOON , Pinyen LIN
IPC分类号: H01L29/06 , H01L29/786 , H01L29/66 , H01L21/8234
CPC分类号: H01L29/0653 , H01L21/823412 , H01L21/823418 , H01L21/823481 , H01L29/0665 , H01L29/66545 , H01L29/66742 , H01L29/78618 , H01L29/78696
摘要: A device includes a first semiconductor structure, a second semiconductor structure, and an isolation structure which is disposed between the first and second semiconductor structures, and which includes a dielectric material having a dielectric constant higher than 8 and lower than 16. A method for manufacturing the device is also disclosed.
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公开(公告)号:US20220157605A1
公开(公告)日:2022-05-19
申请号:US17589315
申请日:2022-01-31
发明人: Shih-Chun HUANG , Chiu-Hsiang CHEN , Ya-Wen YEH , Yu-Tien SHEN , Po-Chin CHANG , Chien-Wen LAI , Wei-Liang LIN , Ya Hui CHANG , Yung-Sung YEN , Li-Te LIN , Pinyen LIN , Ru-Gun LIU , Chin-Hsiang LIN
IPC分类号: H01L21/033 , H01L21/027 , H01L21/311 , H01L21/02 , H01L21/265
摘要: A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.
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公开(公告)号:US20220029002A1
公开(公告)日:2022-01-27
申请号:US17498645
申请日:2021-10-11
发明人: Yi-Chen LO , Li-Te LIN , Yu-Lien HUANG
IPC分类号: H01L29/66 , H01L29/78 , H01L21/02 , H01L21/8234
摘要: A method for fabricating a semiconductor device comprises forming a gate electrode structure over a first region of a semiconductor substrate, and forming a source/drain region on a second region of the semiconductor substrate. The gate electrode structure comprises a metal gate electrode layer, a gate dielectric layer, and gate sidewalls. The second region of the semiconductor substrate is on an opposing side of the metal gate electrode layer. The method for fabricating a semiconductor device further comprises forming an interlayer dielectric layer over the source/drain regions and the gate sidewall, and forming an oxide layer over the source/drain region and the gate sidewall without substantially forming the second oxide layer on the gate electrode layer.
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公开(公告)号:US20210375639A1
公开(公告)日:2021-12-02
申请号:US17403850
申请日:2021-08-16
发明人: Ya-Wen YEH , Yu-Tien SHEN , Shih-Chun HUANG , Po-Chin CHANG , Wei-Liang LIN , Yung-Sung YEN , Wei-Hao WU , Li-Te LIN , Pinyen LIN , Ru-Gun LIU
IPC分类号: H01L21/3213 , H01L21/66
摘要: In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.
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