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公开(公告)号：US20240186148A1
公开(公告)日：2024-06-06
申请号：US18438047
申请日：2024-02-09
发明人： Yen-Hao CHEN , Wei-Han LAI , Ching-Yu CHANG , Chin-Hsiang LIN
IPC分类号： H01L21/321 , H01L21/02 , H01L21/027 , H01L21/3105
CPC分类号： H01L21/32115 , H01L21/02118 , H01L21/02406 , H01L21/02557 , H01L21/0276 , H01L21/31058
摘要： A method of manufacturing a semiconductor device includes forming a first layer of a first planarizing material over a patterned surface of a substrate, forming a second layer of a second planarizing material over the first planarizing layer, crosslinking a portion of the first planarizing material and a portion of the second planarizing material, and removing a portion of the second planarizing material that is not crosslinked. In an embodiment, the method further includes forming a third layer of a third planarizing material over the second planarizing material after removing the portion of the second planarizing material that is not crosslinked. The third planarizing material can include a bottom anti-reflective coating or a spin-on carbon, and an acid or an acid generator. The first planarizing material can include a spin-on carbon, and an acid, a thermal acid generator or a photoacid generator.
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公开(公告)号：US20220157605A1
公开(公告)日：2022-05-19
申请号：US17589315
申请日：2022-01-31
发明人： Shih-Chun HUANG , Chiu-Hsiang CHEN , Ya-Wen YEH , Yu-Tien SHEN , Po-Chin CHANG , Chien-Wen LAI , Wei-Liang LIN , Ya Hui CHANG , Yung-Sung YEN , Li-Te LIN , Pinyen LIN , Ru-Gun LIU , Chin-Hsiang LIN
IPC分类号： H01L21/033 , H01L21/027 , H01L21/311 , H01L21/02 , H01L21/265
摘要： A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.
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公开(公告)号：US20210296303A1
公开(公告)日：2021-09-23
申请号：US17330678
申请日：2021-05-26
发明人： Hung-Wen CHO , Fu-Jye LIANG , Chun-Kuang CHEN , Chih-Tsung SHIH , Li-Jui CHEN , Po-Chung CHENG , Chin-Hsiang LIN
摘要： A layout modification method for fabricating a semiconductor device is provided. The layout modification method includes calculating uniformity of critical dimensions of first and second portions in a patterned layer by using a layout for an exposure manufacturing process to produce the semiconductor device. A width of the first and second portions equals a penumbra size of the exposure manufacturing process. The penumbra size is utilized to indicate which area of the patterned layer is affected by light leakage exposure from another exposure manufacturing process. The layout modification method further includes compensating non-uniformity of the first and second portions of the patterned layer according to the uniformity of critical dimensions to generate a modified layout. The first portion is divided into a plurality of first sub-portions. The second portion is divided into a plurality of second sub-portions. Each second sub-portion is surrounded by two of the first sub-portions.
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4.发明申请公开(公告)号：US20180073144A1
公开(公告)日：2018-03-15
申请号：US15822469
申请日：2017-11-27
发明人： Yen-Shuo SU , Ying XIAO , Chin-Hsiang LIN
IPC分类号： C23C16/50 , C23C16/52 , H01J37/32 , C23C16/455
CPC分类号： C23C16/50 , C23C16/45561 , C23C16/45563 , C23C16/45565 , C23C16/52 , H01J37/3244 , H01J37/32449 , H01J37/32532 , H01J37/32899
摘要： A control system for a plasma treatment apparatus includes a wafer treatment device. The wafer treatment device includes a vapor chamber and an upper electrode assembly. The upper electrode assembly includes a gas distribution plate having a plurality of holes. The upper electrode assembly includes an upper electrode having at least one gas nozzle and at least one controllable valve connected to the at least one gas nozzle for controlling a flow of gas from a gas supply to the holes via the at least one gas nozzle. The at least one gas nozzle is separated from the gate distribution plate by a gap. The control system includes a measurement device configured to measure a thickness profile of a wafer. The control system includes a controller configured to generate a control signal. The at least one controllable valve is configured to be adjusted based on the control signal.
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公开(公告)号：US20240061344A1
公开(公告)日：2024-02-22
申请号：US18499955
申请日：2023-11-01
发明人： Hsu-Ting HUANG , Tung-Chin WU , Shih-Hsiang LO , Chih-Ming LAI , Jue-Chin YU , Ru-Gun LIU , Chin-Hsiang LIN
IPC分类号： G03F7/00 , G06F16/23 , G06F30/392 , G06F30/398 , G06N3/04 , G06N3/08
CPC分类号： G03F7/70441 , G06F16/2379 , G06F30/392 , G06F30/398 , G06N3/04 , G06N3/08
摘要： A method for manufacturing a lithographic mask for an integrated circuit includes performing an optical proximity correction (OPC) process to an integrated circuit mask layout to produce a corrected mask layout. The method further includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout. The method also includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout.
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公开(公告)号：US20230341780A1
公开(公告)日：2023-10-26
申请号：US18200510
申请日：2023-05-22
发明人： Tzu-Yang LIN , Ching-Yu CHANG , Chin-Hsiang LIN
IPC分类号： G03F7/30 , G03F7/38 , G03F7/40 , G03F7/36 , G03F7/32 , G03F7/039 , G03F7/20 , G03F7/004 , G03F7/038
CPC分类号： G03F7/30 , G03F7/0045 , G03F7/0382 , G03F7/0392 , G03F7/0397 , G03F7/2004 , G03F7/32 , G03F7/36 , G03F7/38 , G03F7/40 , B82Y40/00
摘要： A photoresist composition includes a photoactive compound and a polymer. The polymer has a polymer backbone including one or more groups selected from:
The polymer backbone includes at least one group selected from B, C-1, or C-2, wherein ALG is an acid labile group, and X is a linking group.-
公开(公告)号：US20230245889A1
公开(公告)日：2023-08-03
申请号：US18132843
申请日：2023-04-10
发明人： An-Ren ZI , Ching-Yu CHANG , Chin-Hsiang LIN
IPC分类号： H01L21/027 , H01L21/67
CPC分类号： H01L21/0274 , H01L21/67115
摘要： A method of manufacturing a semiconductor device includes forming a first protective layer over an edge portion of a first main surface of a semiconductor substrate. A metal-containing photoresist layer is formed over the first main surface of the semiconductor substrate. The first protective layer is removed, and the metal-containing photoresist layer is selectively exposed to actinic radiation. A second protective layer is formed over the edge portion of the first main surface of the semiconductor substrate. The selectively exposed photoresist layer is developed to form a patterned photoresist layer, and the second protective layer is removed.
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公开(公告)号：US20220285168A1
公开(公告)日：2022-09-08
申请号：US17751361
申请日：2022-05-23
发明人： Ru-Gun LIU , Chih-Ming LAI , Wei-Liang LIN , Yung-Sung YEN , Ken-Hsien HSIEH , Chin-Hsiang LIN
IPC分类号： H01L21/311 , H01L21/027 , H01L21/768
摘要： In a method of forming a groove pattern extending in a first axis in an underlying layer over a semiconductor substrate, a first opening is formed in the underlying layer, and the first opening is extended in the first axis by directional etching to form the groove pattern.
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公开(公告)号：US20220260931A1
公开(公告)日：2022-08-18
申请号：US17733664
申请日：2022-04-29
发明人： Shinn-Sheng YU , Ru-Gun LIU , Hsu-Ting HUANG , Kenji YAMAZOE , Minfeng CHEN , Shuo-Yen CHOU , Chin-Hsiang LIN
IPC分类号： G03F7/20
摘要： A method of manufacturing a semiconductor device includes dividing a number of dies along an x axis in a die matrix in each exposure field in an exposure field matrix delineated on the semiconductor substrate, wherein the x axis is parallel to one edge of a smallest rectangle enclosing the exposure field matrix. A number of dies is divided along a y axis in the die matrix, wherein the y axis is perpendicular to the x axis. Sequences SNx0, SNx1, SNx, SNxr, SNy0, SNy1, SNy, and SNyr are formed. p*(Nbx+1)−2 stepping operations are performed in a third direction and first sequence exposure/stepping/exposure operations and second sequence exposure/stepping/exposure operations are performed alternately between any two adjacent stepping operations as well as before a first stepping operation and after a last stepping operation. A distance of each stepping operation in order follows the sequence SNx.
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公开(公告)号：US20210278762A1
公开(公告)日：2021-09-09
申请号：US17326977
申请日：2021-05-21
发明人： An-Ren ZI , Chin-Hsiang LIN , Ching-Yu CHANG
IPC分类号： G03F7/004 , G03F7/16 , G03F7/38 , H01L21/027 , G03F7/30 , G03F7/42 , G03F7/039 , G03F7/038 , G03F7/11
摘要： A method of forming a photoresist pattern includes forming a protective layer over a photoresist layer formed on a substrate, and selectively exposing the protective layer and the photoresist layer to actinic radiation. The protective layer and the photoresist layer are developed to form a pattern in the photoresist layer, and the protective layer is removed. The protective layer includes a polymer having pendant fluorocarbon groups and pendant acid leaving groups.
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