公开(公告)号：US11979158B2

公开(公告)日：2024-05-07

申请号：US17825704

申请日：2022-05-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Cheng-Yu Lin ,  Yung-Chen Chien ,  Jia-Hong Gao ,  Jerry Chang Jui Kao ,  Hui-Zhong Zhuang

IPC: H03K3/00 ,  H03K3/012 ,  H03K3/037 ,  H03K3/356 ,  H03K3/3562

CPC classification number: H03K3/35625 ,  H03K3/012 ,  H03K3/0372 ,  H03K3/356104

Abstract: An integrated circuit (IC) device includes a master latch circuit having a first clock input and a data output, a slave latch circuit having a second clock input and a data input electrically coupled to the data output of the master latch circuit, and a clock circuit. The clock circuit is electrically coupled to the first clock input by a first electrical connection configured to have a first time delay between the clock circuit and the first clock input. The clock circuit is electrically coupled to the second clock input by a second electrical connection configured to have a second time delay between the clock circuit and the second clock input. The first time delay is longer than the second time delay.

公开(公告)号：US11715733B2

公开(公告)日：2023-08-01

申请号：US17313474

申请日：2021-05-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Ren Chen ,  Cheng-Yu Lin ,  Hui-Zhong Zhuang ,  Yung-Chen Chien ,  Jerry Chang Jui Kao ,  Huang-Yu Chen ,  Chung-Hsing Wang

IPC: H01L27/02 ,  H01L27/092 ,  G06F30/394 ,  H01L21/8238 ,  G06F30/392 ,  H01L23/522

CPC classification number: H01L27/0207 ,  G06F30/392 ,  G06F30/394 ,  H01L21/823871 ,  H01L23/5226 ,  H01L27/092

Abstract: An integrated circuit (IC) device includes a substrate, and a cell over the substrate. The cell includes at least one active region and at least one gate region extending across the at least one active region. The cell further includes at least one input/output (IO) pattern configured to electrically couple one or more of the at least one active region and the at least one gate region to external circuitry outside the cell. The at least one IO pattern extends obliquely to both the at least one active region and the at least one gate region.

公开(公告)号：US12164853B2

公开(公告)日：2024-12-10

申请号：US17574048

申请日：2022-01-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Anurag Verma ,  Chi-Chun Liang ,  Meng-Kai Hsu ,  Cheng-Yu Lin ,  Pochun Wang ,  Hui-Zhong Zhuang

IPC: G06F30/392 ,  G06F30/394 ,  G06F119/18

Abstract: The present disclosure provides a method and an apparatus for generating a layout of a semiconductor device. The method includes placing a first cell and a second cell adjacent to the first cell, placing a first conductive pattern in a first track of the first cell extending in a first direction, wherein the first conductive pattern is configured as an input terminal or an output terminal of the first cell, placing a second conductive pattern in a first track of the second cell extending in the first direction, wherein the second conductive pattern is configured as an input terminal or an output terminal of the second cell, and aligning the first conductive pattern with the second conductive pattern.

公开(公告)号：US12014982B2

公开(公告)日：2024-06-18

申请号：US17463203

申请日：2021-08-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Cheng-Yu Lin ,  Jung-Chan Yang ,  Hui-Zhong Zhuang ,  Sheng-Hsiung Chen ,  Kuo-Nan Yang ,  Chih-Liang Chen ,  Lee-Chung Lu

IPC: G06F30/30 ,  G06F30/347 ,  G06F30/392 ,  G06F30/394 ,  H01L23/50 ,  H01L23/528 ,  H01L27/07 ,  H01L27/118 ,  H01L29/417 ,  H01L27/02

CPC classification number: H01L23/528 ,  G06F30/347 ,  G06F30/392 ,  G06F30/394 ,  H01L23/50 ,  H01L27/07 ,  H01L27/11807 ,  H01L29/41733 ,  H01L27/0207 ,  H01L2027/11879 ,  H01L2027/11881 ,  H01L2027/11887

Abstract: An IC device includes first and second cells adjacent each other and over a substrate. The first cell includes a first IO pattern along a first track among a plurality of tracks in a first metal layer, the plurality of tracks elongated along a first axis and spaced from each other along a second axis. The second cell includes a plurality of conductive patterns along corresponding different tracks among the plurality of tracks in the first metal layer, each of the plurality of conductive patterns being an IO pattern of the second cell or a floating conductive pattern. The first metal layer further includes a first connecting pattern along the first track and connects the first IO pattern and a second IO pattern of the second cell. The second IO pattern is one of the plurality of conductive patterns of the second cell and is along the first track.

公开(公告)号：US12142637B2

公开(公告)日：2024-11-12

申请号：US17575590

申请日：2022-01-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Cheng-Yu Lin ,  Yi-Lin Fan ,  Hui-Zhong Zhuang ,  Sheng-Hsiung Chen ,  Jerry Chang Jui Kao ,  Xiangdong Chen

IPC: H01L29/06 ,  H01L23/522 ,  H01L29/40 ,  H01L29/423

Abstract: A cell region of a semiconductor device includes a first and second isolation dummy gates extending along a first direction. The semiconductor device further includes a first gate extending along the first direction and between the first isolation dummy gate and the second isolation dummy gate. The semiconductor device includes a second gate extending along the first direction, the second gate being between the first isolation dummy gate and the second isolation dummy gate relative to a second direction perpendicular to the first direction. The semiconductor device also includes a first active region and a second active region. The first active region extending in the second direction between the first isolation dummy gate and the second isolation dummy gate. The first active region has a first length in the second direction, and the second active region has a second length in the second direction different from the first length.