公开(公告)号：US11101353B2

公开(公告)日：2021-08-24

申请号：US16387043

申请日：2019-04-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Hsien Huang ,  Chang-Ting Chung ,  Wei-Cheng Lin ,  Wei-Jung Lin ,  Chih-Wei Chang

IPC: H01L29/40 ,  H01L21/02 ,  H01L21/768 ,  H01L29/66 ,  H01L29/417 ,  H01L21/311 ,  H01L21/285 ,  H01L21/321 ,  H01L21/3065 ,  H01L29/78 ,  H01L29/08

Abstract: Methods of forming contacts for source/drain regions and a contact plug for a gate stack of a finFET device are disclosed herein. Methods include etching a contact opening through a dielectric layer to expose surfaces of a first source/drain contact and repairing silicon oxide structures along sidewall surfaces of the contact opening and along planar surfaces of the dielectric layer to prevent selective loss defects from occurring during a subsequent selective deposition of conductive fill materials and during subsequent etching of other contact openings. The methods further include performing a selective bottom-up deposition of conductive fill material to form a second source/drain contact. According to some of the methods, once the second source/drain contact has been formed, the contact plug may be formed over the gate stack.

公开(公告)号：US20200335588A1

公开(公告)日：2020-10-22

申请号：US16387043

申请日：2019-04-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Hsien Huang ,  Chang-Ting Chung ,  Wei-Cheng Lin ,  Wei-Jung Lin ,  Chih-Wei Chang

IPC: H01L29/40 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/285 ,  H01L29/66 ,  H01L29/417

Abstract: Methods of forming contacts for source/drain regions and a contact plug for a gate stack of a finFET device are disclosed herein. Methods include etching a contact opening through a dielectric layer to expose surfaces of a first source/drain contact and repairing silicon oxide structures along sidewall surfaces of the contact opening and along planar surfaces of the dielectric layer to prevent selective loss defects from occurring during a subsequent selective deposition of conductive fill materials and during subsequent etching of other contact openings. The methods further include performing a selective bottom-up deposition of conductive fill material to form a second source/drain contact. According to some of the methods, once the second source/drain contact has been formed, the contact plug may be formed over the gate stack.

公开(公告)号：US12237218B2

公开(公告)日：2025-02-25

申请号：US17738009

申请日：2022-05-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chang-Ting Chung ,  Shih-Wei Yeh ,  Kai-Chieh Yang ,  Yu-Ting Wen ,  Yu-Chen Ko ,  Ya-Yi Cheng ,  Min-Hsiu Hung ,  Chun-Hsien Huang ,  Wei-Jung Lin ,  Chih-Wei Chang ,  Ming-Hsing Tsai

IPC: H01L21/768 ,  H01L21/3213 ,  H01L29/40 ,  H01L29/45 ,  H10B10/00

Abstract: A method of fabricating a contact structure includes the following steps. An opening is formed in a dielectric layer. A conductive material layer is formed within the opening and on the dielectric layer, wherein the conductive material layer includes a bottom section having a first thickness and a top section having a second thickness, the second thickness is greater than the first thickness. A first treatment is performed on the conductive material layer to form a first oxide layer on the bottom section and on the top section of the conductive material layer. A second treatment is performed to remove at least portions of the first oxide layer and at least portions of the conductive material layer, wherein after performing the second treatment, the bottom section and the top section of the conductive material layer have substantially equal thickness.

公开(公告)号：US11929314B2

公开(公告)日：2024-03-12

申请号：US17200024

申请日：2021-03-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Hsien Huang ,  Peng-Fu Hsu ,  Yu-Syuan Cai ,  Min-Hsiu Hung ,  Chen-Yuan Kao ,  Ken-Yu Chang ,  Chun-I Tsai ,  Chia-Han Lai ,  Chih-Wei Chang ,  Ming-Hsing Tsai

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L21/4828 ,  H01L23/49838 ,  H01L24/29 ,  H01L2224/29184

Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.

公开(公告)号：US09368357B2

公开(公告)日：2016-06-14

申请号：US14982592

申请日：2015-12-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Wei Chang ,  Hung-Chang Hsu ,  Chun-Hsien Huang ,  Yu-Hung Lin ,  Li-Wei Chu ,  Sheng-Hsuan Lin ,  Wei-Jung Lin ,  Yu-Shiuan Wang

IPC: H01L21/00 ,  H01L21/44 ,  H01L21/285 ,  H01L21/306 ,  H01L21/265 ,  H01L21/324 ,  H01L21/225 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L21/28518 ,  H01L21/02063 ,  H01L21/02359 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method includes etching a dielectric layer to form an opening, with an underlying region underlying the dielectric layer exposed to the opening, and performing a bombardment to bombard a surface region of the underlying region through the opening. After the bombardment, the surface region is reacted with a process gas to form a reaction layer. An anneal is then performed to remove the reaction layer.

Abstract translation: 一种方法包括蚀刻电介质层以形成开口，其中介质层下方的下部区域暴露于开口，并且通过开口进行轰击以轰击下面区域的表面区域。 轰击后，表面区域与处理气体反应形成反应层。 然后进行退火以除去反应层。

公开(公告)号：US20160126102A1

公开(公告)日：2016-05-05

申请号：US14982592

申请日：2015-12-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Wei Chang ,  Hung-Chang Hsu ,  Chun-Hsien Huang ,  Yu-Hung Lin ,  Li-Wei Chu ,  Sheng-Hsuan Lin ,  Wei-Jung Lin ,  Yu-Shiuan Wang

IPC: H01L21/285 ,  H01L21/265 ,  H01L21/768 ,  H01L21/225 ,  H01L29/66 ,  H01L21/306 ,  H01L21/324

CPC classification number: H01L21/28518 ,  H01L21/02063 ,  H01L21/02359 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method includes etching a dielectric layer to form an opening, with an underlying region underlying the dielectric layer exposed to the opening, and performing a bombardment to bombard a surface region of the underlying region through the opening. After the bombardment, the surface region is reacted with a process gas to form a reaction layer. An anneal is then performed to remove the reaction layer.

Abstract translation: 一种方法包括蚀刻电介质层以形成开口，其中介质层下方的下部区域暴露于开口，并且通过开口进行轰击以轰击下面区域的表面区域。 轰击后，表面区域与处理气体反应形成反应层。 然后进行退火以除去反应层。

公开(公告)号：US11410880B2

公开(公告)日：2022-08-09

申请号：US16392067

申请日：2019-04-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Hsien Huang ,  I-Li Chen ,  Pin-Wen Chen ,  Yuan-Chen Hsu ,  Wei-Jung Lin ,  Chih-Wei Chang ,  Ming-Hsing Tsai

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: A method includes forming a first metallic feature, forming a dielectric layer over the first metallic feature, etching the dielectric layer to form an opening, with a top surface of the first metallic feature being exposed through the opening, and performing a first treatment on the top surface of the first metallic feature. The first treatment is performed through the opening, and the first treatment is performed using a first process gas. After the first treatment, a second treatment is performed through the opening, and the second treatment is performed using a second process gas different from the first process gas. A second metallic feature is deposited in the opening.

公开(公告)号：US20200343135A1

公开(公告)日：2020-10-29

申请号：US16392067

申请日：2019-04-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Hsien Huang ,  I-Li Chen ,  Pin-Wen Chen ,  Yuan-Chen Hsu ,  Wei-Jung Lin ,  Chih-Wei Chang ,  Ming-Hsing Tsai

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A method includes forming a first metallic feature, forming a dielectric layer over the first metallic feature, etching the dielectric layer to form an opening, with a top surface of the first metallic feature being exposed through the opening, and performing a first treatment on the top surface of the first metallic feature. The first treatment is performed through the opening, and the first treatment is performed using a first process gas. After the first treatment, a second treatment is performed through the opening, and the second treatment is performed using a second process gas different from the first process gas. A second metallic feature is deposited in the opening.

公开(公告)号：US09230795B1

公开(公告)日：2016-01-05

申请号：US14527300

申请日：2014-10-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Shiuan Wang ,  Hung-Chang Hsu ,  Li-Wei Chu ,  Sheng-Hsuan Lin ,  Chun-Hsien Huang ,  Yu-Hung Lin ,  Chih-Wei Chang ,  Wei-Jung Lin

IPC: H01L21/00 ,  H01L21/44 ,  H01L21/02

CPC classification number: H01L21/28518 ,  H01L21/02063 ,  H01L21/02359 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method includes etching a dielectric layer to form an opening, with an underlying region underlying the dielectric layer exposed to the opening, and performing a bombardment to bombard a surface region of the underlying region through the opening. After the bombardment, the surface region is reacted with a process gas to form a reaction layer. An anneal is then performed to remove the reaction layer.

公开(公告)号：US20250040213A1

公开(公告)日：2025-01-30

申请号：US18360588

申请日：2023-07-27

Applicant: Taiwan Semiconductor Manufacturing Company Ltd.

Inventor： Yi-Hsiang Chao ,  Peng-Hao Hsu ,  Yu-Shiuan Wang ,  Chi-Yuan Chen ,  Yu-Hsiang Liao ,  Chun-Hsien Huang ,  Hung-Chang Hsu ,  Wei-Jung Lin ,  Chih-Wei Chang ,  Ming-Hsing Tsai

IPC: H01L29/40 ,  H01L21/3205 ,  H01L29/417 ,  H01L29/45

Abstract: A semiconductor structure includes a source/drain feature in the semiconductor layer. The semiconductor structure includes a dielectric layer over the source/drain feature. The semiconductor structure includes a silicide layer over the source/drain feature. The semiconductor structure includes a barrier layer over the silicide layer. The semiconductor structure includes a seed layer over the barrier layer. The semiconductor structure includes a metal layer between a sidewall of the seed layer and a sidewall of the dielectric layer, a sidewall of each of the silicide layer, the barrier layer, and the metal layer directly contacting the sidewall of the dielectric layer. The semiconductor structure includes a source/drain contact over the seed layer.