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公开(公告)号：US20240324235A1
公开(公告)日：2024-09-26
申请号：US18677952
申请日：2024-05-30
发明人： Chun-Chieh Lu , Han-Jong Chia , Sai-Hooi Yeong , Bo-Feng Young , Yu-Ming Lin
IPC分类号： H10B51/30 , H01L29/66 , H01L29/786 , H10B51/20
CPC分类号： H10B51/30 , H01L29/66969 , H01L29/7869 , H01L29/78696 , H10B51/20
摘要： Provided is a ferroelectric memory device having a dielectric layer vertically interleaved between a first conductive line and a second conductive line. A first ferroelectric portion is arranged along a sidewall of the first conductive line and a second ferroelectric portion is arranged along a sidewall of the second conductive line. A channel layer is arranged along sides of the dielectric layer, the first conductive line, and the second conductive line. A topmost surface of the first ferroelectric portion is vertically separated from a bottommost surface of the second ferroelectric portion by the channel layer.
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公开(公告)号：US11991887B2
公开(公告)日：2024-05-21
申请号：US17313254
申请日：2021-05-06
发明人： Chenchen Jacob Wang , Chun-Chieh Lu , Yi-Ching Liu
IPC分类号： H10B51/40 , G11C11/22 , G11C16/08 , H01L23/522 , H10B43/27 , H10B43/40 , H10B51/20 , H10B43/10 , H10B51/10
CPC分类号： H10B51/40 , G11C11/2255 , G11C16/08 , H01L23/5226 , H10B43/27 , H10B43/40 , H10B51/20 , H10B43/10 , H10B51/10
摘要： Three-dimensional memories are provided. A three-dimensional memory includes a memory cell array, a first interconnect structure, a bit line decoder and a second interconnect structure. The bit line decoder is formed under the memory cell array and the first interconnect structure. The memory cell array includes a plurality of memory cells formed in a plurality of levels stacked in a first direction. The first interconnect structure includes at least one bit line extending in a second direction that is perpendicular to the first direction. The bit line includes a plurality of sub-bit lines stacked in the first direction. Each of the sub-bit lines is coupled to the memory cells that are arranged in a line in the corresponding level of the memory cell array. The second interconnect structure is configured to connect the bit line to the bit line decoder passing through the first interconnect structure.
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公开(公告)号：US11916144B2
公开(公告)日：2024-02-27
申请号：US17883699
申请日：2022-08-09
IPC分类号： H01L29/78 , H01L29/66 , H01L29/786 , H01L21/447 , H01L21/383 , H01L29/49 , H01L27/12
CPC分类号： H01L29/78391 , H01L21/383 , H01L21/447 , H01L29/4908 , H01L29/66969 , H01L29/7869 , H01L27/1207
摘要： In some embodiments of the present disclosure, a method for forming a semiconductor device is described. A semiconductor layer is formed and a dielectric layer is formed. A pressurized treatment is performed to transform the semiconductor layer into a low-doping semiconductor layer and transform the dielectric layer into a crystalline ferroelectric layer. A gate layer is formed. An insulating layer is formed over the gate layer, the crystalline ferroelectric layer and the low-doping semiconductor layer. Contact openings are formed in the insulating layer exposing portions of the low-doping semiconductor layer. Source and drain terminals are formed on the low-doping semiconductor layer.
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公开(公告)号：US11574928B2
公开(公告)日：2023-02-07
申请号：US17243732
申请日：2021-04-29
IPC分类号： H01L27/1159 , H01L27/11587 , H01L29/417 , H01L29/78 , H01L21/28 , H01L29/66
摘要： A semiconductor memory structure includes a fin structure formed over a substrate. The structure also includes a gate structure formed across the fin structure. The structure also includes spacers formed over opposite sides of the gate structure. The structure also includes source drain epitaxial structures formed on opposite sides of the gate structure beside the spacers. The gate structure includes a III-V ferroelectric layer formed between an interfacial layer and a gate electrode layer.
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公开(公告)号：US20210375931A1
公开(公告)日：2021-12-02
申请号：US17113106
申请日：2020-12-07
发明人： Chun-Chieh Lu , Georgios Vellianitis , Marcus Johannes Henricus Van Dal , Sai-Hooi Yeong , Yu-Ming Lin
IPC分类号： H01L27/11597 , H01L27/1159 , H01L29/51 , H01L21/28
摘要： A device includes a multi-layer stack, a channel layer, a ferroelectric layer and buffer layers. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. The ferroelectric layer is disposed between the channel layer and each of the plurality of conductive layers and the plurality of dielectric layers. The buffer layers include a metal oxide, and one of the buffer layers is disposed between the ferroelectric layer and each of the plurality of dielectric layers.
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公开(公告)号：US20210066627A1
公开(公告)日：2021-03-04
申请号：US16837261
申请日：2020-04-01
发明人： Chao-Ching Cheng , Tzu-Ang Chao , Chun-Chieh Lu , Hung-Li Chiang , Tzu-Chiang Chen , Lain-Jong Li
IPC分类号： H01L51/05 , H01L51/00 , H01L21/02 , H01L29/66 , H01L29/06 , H01L29/24 , H01L29/423 , H01L29/786
摘要： A method includes forming a first low-dimensional layer over an isolation layer, forming a first insulator over the first low-dimensional layer, forming a second low-dimensional layer over the first insulator, forming a second insulator over the second low-dimensional layer, and patterning the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator into a protruding fin. Remaining portions of the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator form a first low-dimensional strip, a first insulator strip, a second low-dimensional strip, and a second insulator strip, respectively. A transistor is then formed based on the protruding fin.
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公开(公告)号：US20240206185A1
公开(公告)日：2024-06-20
申请号：US18591047
申请日：2024-02-29
发明人： Chun-Chieh Lu , Sai-Hooi Yeong , Bo-Feng Young , Yu-Ming Lin , Chih-Yu Chang
IPC分类号： H10B51/20 , H01L21/02 , H01L21/383 , H01L21/425 , H01L21/477 , H01L29/24 , H10B51/30
CPC分类号： H10B51/20 , H01L21/02565 , H01L21/383 , H01L21/425 , H01L21/477 , H01L29/24 , H10B51/30
摘要： The present disclosure relates to an integrated chip device. The integrated chip device includes a plurality of conductive lines disposed over a substrate. The plurality of conductive lines are stacked onto one another and are separated from one another by dielectric layers interleaved between adjacent ones of the plurality of conductive lines. A ferroelectric layer is along sidewalls of the plurality of conductive lines and the dielectric layers. The ferroelectric layer separates a channel layer from the plurality of conductive lines. A species is disposed within the ferroelectric layer. The species has a concentration that decreases from the channel layer towards a surface of the ferroelectric layer that faces away from the channel layer.
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公开(公告)号：US11950427B2
公开(公告)日：2024-04-02
申请号：US17869824
申请日：2022-07-21
发明人： Chun-Chieh Lu , Sai-Hooi Yeong , Bo-Feng Young , Yu-Ming Lin , Chih-Yu Chang
IPC分类号： H01L21/00 , H01L21/02 , H01L21/383 , H01L21/425 , H01L21/477 , H01L29/24 , H10B51/20 , H10B51/30
CPC分类号： H10B51/20 , H01L21/02565 , H01L21/383 , H01L21/425 , H01L21/477 , H01L29/24 , H10B51/30
摘要： A memory cell includes a transistor over a semiconductor substrate. The transistor includes a ferroelectric layer arranged along a sidewall of a word line. The ferroelectric layer includes a species with valence of 5, valence of 7, or a combination thereof. An oxide semiconductor layer is electrically coupled to a source line and a bit line. The ferroelectric layer is disposed between the oxide semiconductor layer and the word line.
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公开(公告)号：US20230371257A1
公开(公告)日：2023-11-16
申请号：US18359181
申请日：2023-07-26
发明人： Chun-Chieh Lu , Sai-Hooi Yeong , Yu-Ming Lin
IPC分类号： H01L29/76 , H01L23/522
CPC分类号： H10B43/27 , H01L23/5221 , H10B41/10 , H10B41/27 , H10B43/10
摘要： A process of forming a three-dimensional (3D) memory array includes forming a stack having a plurality of conductive layers of carbon-based material separated by dielectric layers. Etching trenches in the stack divides the conductive layers into conductive strips. The resulting structure includes a two-dimensional array of horizontal conductive strips. Memory cells may be distributed along the length of each strip to provide a 3D array. The conductive strips together with additional conductive structure that may have a vertical or horizontal orientation allow the memory cells to be addressed individually. Forming the conductive layers with carbon-based material facilitate etching the trenches to a high aspect ratio. Accordingly, forming the conductive layers of carbon-based material enables the memory array to have more layers or to have a higher area density.
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公开(公告)号：US20230328997A1
公开(公告)日：2023-10-12
申请号：US18336105
申请日：2023-06-16
发明人： Chun-Chieh Lu , Sai-Hooi Yeong , Bo-Feng Young , Yu-Ming Lin , Chih-Yu Chang
CPC分类号： H10B51/20 , H01L21/02565 , H01L29/24 , H10B51/30
摘要： The present disclosure, in some embodiments, relates to a ferroelectric memory device. The ferroelectric memory device includes a multi-layer stack disposed on a substrate. The multi-layer stack has a plurality of conductive layers and a plurality of dielectric layers stacked alternately. A channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. A ferroelectric layer is disposed between the channel layer and both of the plurality of conductive layers and the plurality of dielectric layers. A plurality of oxygen scavenging layers are disposed along sidewalls of the plurality of conductive layer. The plurality of oxygen scavenging layers laterally separate the ferroelectric layer from the plurality of conductive layers.
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