公开(公告)号：US09053288B1

公开(公告)日：2015-06-09

申请号：US14231273

申请日：2014-03-31

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yao-Jen Hsieh ,  Kai-Ming Liu

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： A method includes extracting multiple-patterning group assignment information of one or more layout patterns from a layout design. The layout design corresponds to a circuit design, and the one or more layout patterns corresponding to a node of the circuit design. Whether the extracted multiple-patterning group assignment information is consistent with a set of multiple-patterning group assignment constraints of the node is determined by a hardware processor.

摘要翻译： 一种方法包括从布局设计中提取一个或多个布局图案的多图案化组分配信息。 布局设计对应于电路设计，并且一个或多个布局图案对应于电路设计的节点。 提取的多图案化组分配信息是否与节点的一组多图案化组分配约束一致由硬件处理器确定。

公开(公告)号：US20140282326A1

公开(公告)日：2014-09-18

申请号：US13840789

申请日：2013-03-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shih Hsin Chen ,  Kai-Ming Liu

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  H01L29/6681

摘要： Methods for standard cells using finFET standard cell structures with polysilicon on OD edges. Standard cells are defined using finFET transistors and having gate structures forming a transistor at an intersection with a semiconductor fin. Polysilicon dummy structures are formed on the edges of the active areas or OD areas of the standard cells. In a design flow, a pre-layout netlist schematic for the standard cells includes a three terminal MOS device corresponding to the polysilicon dummy structure on the edges of the standard cell. After an automated place and route process forms a device layout using the standard cells, a post layout netlist is extracted. Where two standard cells abut one another, a single polysilicon dummy structure is formed on the common boundary. A layout versus schematic comparison is then performed comparing the pre-layout netlist and the post-layout netlist to verify the layout obtained. Additional methods are disclosed.

摘要翻译： 在OD边缘上使用具有多晶硅的finFET标准单元结构的标准电池的方法。 使用finFET晶体管限定标准单元，并且在与半导体鳍片的交叉点处形成晶体管的栅极结构。 多晶硅虚拟结构形成在标准单元的有源区域或OD区域的边缘上。 在设计流程中，用于标准单元的预布局网表示意图包括对应于标准单元边缘上的多晶硅虚拟结构的三端MOS器件。 在使用标准单元形成设备布局的自动化位置和路线过程之后，提取一个布局网表。 当两个标准单元彼此邻接时，在公共边界上形成单个多晶硅虚拟结构。 然后对布局前的网表和布局后的网表进行布局与原理图比较，以验证所获得的布局。 公开了另外的方法。

公开(公告)号：US09495506B2

公开(公告)日：2016-11-15

申请号：US14733332

申请日：2015-06-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih Hsin Chen ,  Kai-Ming Liu

IPC分类号： G06F17/50 ,  H01L29/00 ,  H01L29/66

CPC分类号： G06F17/5081 ,  G06F17/5009 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/02 ,  G06F2217/06 ,  G06F2217/12 ,  H01L29/00 ,  H01L29/6681

摘要： Methods for verifying the layout for standard cells using finFET standard cell structures with polysilicon on cell edges. Standard cells are defined using finFET transistors. Polysilicon dummy structures are formed on the edges of the active areas of the standard cells. Where two standard cells abut a single polysilicon dummy structure is formed. In a design flow, a pre-layout netlist schematic for the standard cells is formed that does not include devices corresponding to the polysilicon dummy structures. After an automated place and route process forms a device layout using the standard cells, a post layout netlist schematic is extracted including MOS devices corresponding to the polysilicon dummy structures. A layout versus schematic comparison is then performed, but during the comparison MOS devices corresponding to the polysilicon dummy structures are filtered from the post-layout netlist and are not compared. Additional methods are disclosed.

摘要翻译： 使用finFET标准单元结构验证标准单元布局的方法，其中多晶硅在单元边缘。 使用finFET晶体管来限定标准单元。 多晶硅虚拟结构形成在标准单元的有效区域的边缘上。 其中形成两个标准单元邻接单个多晶硅虚拟结构。 在设计流程中，形成标准单元的预布局网表示意图，其不包括对应于多晶硅虚拟结构的器件。 在使用标准单元形成设备布局的自动放置和布线处理之后，提取包括对应于多晶硅虚拟结构的MOS器件的布局布线图示意图。 然后执行布局与原理图比较，但是在比较期间，对应于多晶硅虚拟结构的MOS器件从布局后网络表中被过滤，并且不进行比较。 公开了另外的方法。

公开(公告)号：US09331066B2

公开(公告)日：2016-05-03

申请号：US14163342

申请日：2014-01-24

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Ming-Huei Tsai ,  Yao-Jen Hsieh ,  Kai-Ming Liu

IPC分类号： G06F17/50 ,  H01L27/02

CPC分类号： H01L27/0259 ,  G06F17/5036 ,  G06F17/5068 ,  G06F17/5081

摘要： A method of detecting a parasitic transistor detecting is provided. The method includes extracting several diodes from a selected area, selecting at least one diode pair from the diodes in accordance with signals connected to the diodes, and filtering the at least one diode pair in accordance with a threshold distance to determine whether at least one parasitic transistor is obtained.

摘要翻译： 提供一种检测寄生晶体管检测的方法。 该方法包括从所选择的区域提取几个二极管，根据连接到二极管的信号从二极管中选择至少一个二极管对，并根据阈值距离对至少一个二极管对进行滤波，以确定是否至少有一个寄生 获得晶体管。

公开(公告)号：US11387177B2

公开(公告)日：2022-07-12

申请号：US16442955

申请日：2019-06-17

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Chin-Her Chien ,  Po-Hsiang Huang ,  Cheng-Hung Yeh ,  Tai-Yu Wang ,  Ming-Ke Tsai ,  Yao-Hsien Tsai ,  Kai-Yun Lin ,  Chin-Yuan Huang ,  Kai-Ming Liu ,  Fong-Yuan Chang ,  Chin-Chou Liu ,  Yi-Kan Cheng

IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

摘要： A package structure and a method for forming the same are provided. The package structure includes a die, a first molding surrounding the die, a first redistribution layer (RDL), an interposer disposed over the first RDL, a second molding surrounding the interposer, a first via, and a second RDL. The first RDL includes a first dielectric layer disposed over the die and the first molding, and a first interconnect structure surrounded by the first dielectric layer and electrically connected to the die. The interposer is electrically connected to the die through the first interconnect structure. The first via extends through and within the second molding and is adjacent to the interposer. The second RDL includes a second dielectric layer disposed over the interposer and the second molding, and a second interconnect structure surrounded by the second dielectric layer and electrically connected to the via and the interposer.

公开(公告)号：US20150302136A1

公开(公告)日：2015-10-22

申请号：US14733332

申请日：2015-06-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih Hsin Chen ,  Kai-Ming Liu

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5009 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/02 ,  G06F2217/06 ,  G06F2217/12 ,  H01L29/00 ,  H01L29/6681

摘要： Methods for verifying the layout for standard cells using finFET standard cell structures with polysilicon on cell edges. Standard cells are defined using finFET transistors. Polysilicon dummy structures are formed on the edges of the active areas of the standard cells. Where two standard cells abut a single polysilicon dummy structure is formed. In a design flow, a pre-layout netlist schematic for the standard cells is formed that does not include devices corresponding to the polysilicon dummy structures. After an automated place and route process forms a device layout using the standard cells, a post layout netlist schematic is extracted including MOS devices corresponding to the polysilicon dummy structures. A layout versus schematic comparison is then performed, but during the comparison MOS devices corresponding to the polysilicon dummy structures are filtered from the post-layout netlist and are not compared. Additional methods are disclosed.

摘要翻译： 使用finFET标准单元结构验证标准单元布局的方法，其中多晶硅在单元边缘。 使用finFET晶体管来限定标准单元。 多晶硅虚拟结构形成在标准单元的有效区域的边缘上。 其中形成两个标准单元邻接单个多晶硅虚拟结构。 在设计流程中，形成标准单元的预布局网表示意图，其不包括对应于多晶硅虚拟结构的器件。 在使用标准单元形成设备布局的自动放置和布线处理之后，提取包括对应于多晶硅虚拟结构的MOS器件的布局布线图示意图。 然后执行布局与原理图比较，但是在比较期间，对应于多晶硅虚拟结构的MOS器件从布局后网络表中被过滤，并且不进行比较。 公开了另外的方法。

公开(公告)号：US20140282325A1

公开(公告)日：2014-09-18

申请号：US13840221

申请日：2013-03-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shih Hsin Chen ,  Kai-Ming Liu

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5009 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/02 ,  G06F2217/06 ,  G06F2217/12 ,  H01L29/00 ,  H01L29/6681

摘要： Methods for verifying the layout for standard cells using finFET standard cell structures with polysilicon on cell edges. Standard cells are defined using finFET transistors. Polysilicon dummy structures are formed on the edges of the active areas of the standard cells. Where two standard cells abut a single polysilicon dummy structure is formed. In a design flow, a pre-layout netlist schematic for the standard cells is formed that does not include devices corresponding to the polysilicon dummy structures. After an automated place and route process forms a device layout using the standard cells, a post layout netlist schematic is extracted including MOS devices corresponding to the polysilicon dummy structures. A layout versus schematic comparison is then performed, but during the comparison MOS devices corresponding to the polysilicon dummy structures are filtered from the post-layout netlist and are not compared. Additional methods are disclosed.

摘要翻译： 使用finFET标准单元结构验证标准单元布局的方法，其中多晶硅在单元边缘。 使用finFET晶体管来限定标准单元。 多晶硅虚拟结构形成在标准单元的有效区域的边缘上。 其中形成两个标准单元邻接单个多晶硅虚拟结构。 在设计流程中，形成标准单元的预布局网表示意图，其不包括对应于多晶硅虚拟结构的器件。 在使用标准单元形成设备布局的自动放置和布线处理之后，提取包括对应于多晶硅虚拟结构的MOS器件的布局布线图示意图。 然后执行布局与原理图比较，但是在比较期间，对应于多晶硅虚拟结构的MOS器件从布局后网络表中被过滤，并且不进行比较。 公开了另外的方法。

公开(公告)号：US09747409B2

公开(公告)日：2017-08-29

申请号：US14863900

申请日：2015-09-24

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Wei-Yang Lin ,  Kai-Ming Liu

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5009

摘要： A method performed by at least one processor comprises the steps of: generating a layout data of a chip comprising transistors; determining heat-related parameters for the transistors based on the locations thereof in the layout data; generating a netlist data comprising the heat-related parameters; performing a post-layout simulation based on the netlist data; and verifying whether the post-layout simulation meets a design specification.

公开(公告)号：US20150154339A9

公开(公告)日：2015-06-04

申请号：US13840221

申请日：2013-03-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shih Hsin Chen ,  Kai-Ming Liu

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5009 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/02 ,  G06F2217/06 ,  G06F2217/12 ,  H01L29/00 ,  H01L29/6681

摘要： Methods for verifying the layout for standard cells using finFET standard cell structures with polysilicon on cell edges. Standard cells are defined using finFET transistors. Polysilicon dummy structures are formed on the edges of the active areas of the standard cells. Where two standard cells abut a single polysilicon dummy structure is formed. In a design flow, a pre-layout netlist schematic for the standard cells is formed that does not include devices corresponding to the polysilicon dummy structures. After an automated place and route process forms a device layout using the standard cells, a post layout netlist schematic is extracted including MOS devices corresponding to the polysilicon dummy structures. A layout versus schematic comparison is then performed, but during the comparison MOS devices corresponding to the polysilicon dummy structures are filtered from the post-layout netlist and are not compared. Additional methods are disclosed.

摘要翻译： 使用finFET标准单元结构验证标准单元布局的方法，其中多晶硅在单元边缘。 使用finFET晶体管来限定标准单元。 多晶硅虚拟结构形成在标准单元的有效区域的边缘上。 其中形成两个标准单元邻接单个多晶硅虚拟结构。 在设计流程中，形成标准单元的预布局网表示意图，其不包括对应于多晶硅虚拟结构的器件。 在使用标准单元形成设备布局的自动放置和布线处理之后，提取包括对应于多晶硅虚拟结构的MOS器件的布局布线图示意图。 然后执行布局与原理图比较，但是在比较期间，对应于多晶硅虚拟结构的MOS器件从布局后网络表中被过滤，并且不进行比较。 公开了另外的方法。

公开(公告)号：US08943455B2

公开(公告)日：2015-01-27

申请号：US13840789

申请日：2013-03-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih Hsin Chen ,  Kai-Ming Liu

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  H01L29/6681

摘要： Methods for standard cells using finFET standard cell structures with polysilicon on OD edges. Standard cells are defined using finFET transistors and having gate structures forming a transistor at an intersection with a semiconductor fin. Polysilicon dummy structures are formed on the edges of the active areas or OD areas of the standard cells. In a design flow, a pre-layout netlist schematic for the standard cells includes a three terminal MOS device corresponding to the polysilicon dummy structure on the edges of the standard cell. After an automated place and route process forms a device layout using the standard cells, a post layout netlist is extracted. Where two standard cells abut one another, a single polysilicon dummy structure is formed on the common boundary. A layout versus schematic comparison is then performed comparing the pre-layout netlist and the post-layout netlist to verify the layout obtained. Additional methods are disclosed.

摘要翻译： 在OD边缘上使用具有多晶硅的finFET标准单元结构的标准电池的方法。 使用finFET晶体管限定标准单元，并且在与半导体鳍片的交叉点处形成晶体管的栅极结构。 多晶硅虚拟结构形成在标准单元的有源区域或OD区域的边缘上。 在设计流程中，用于标准单元的预布局网表示意图包括对应于标准单元边缘上的多晶硅虚拟结构的三端MOS器件。 在使用标准单元形成设备布局的自动化位置和路线过程之后，提取一个布局网表。 当两个标准单元彼此邻接时，在公共边界上形成单个多晶硅虚拟结构。 然后对布局前的网表和布局后的网表进行布局与原理图比较，以验证所获得的布局。 公开了另外的方法。