公开(公告)号：US20240357804A1

公开(公告)日：2024-10-24

申请号：US18757580

申请日：2024-06-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： MENG-SHENG CHANG ,  CHIA-EN HUANG ,  YAO-JEN YANG ,  YIH WANG

IPC: H10B20/20 ,  G06F12/14 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H10B99/00

CPC classification number: H10B20/20 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823456 ,  H01L27/0886 ,  H01L29/42316 ,  H01L29/7851 ,  H10B99/00 ,  G06F12/1433

Abstract: A memory device includes: a substrate; a semiconductor fin over the substrate in a first direction; a first gate electrode and a second gate electrode over the substrate in a second direction, the semiconductor fin extending through the second gate electrode and terminating at the first gate electrode; a first gate dielectric layer arranged between the semiconductor fin and the first gate electrode; and a second gate dielectric layer arranged between the semiconductor fin and the second gate electrode. The second gate electrode is configured as a read transistor of a first memory cell, in which the second gate dielectric layer is kept intact, and the first gate electrode is configured as a program transistor of the first memory cell, in which an occurrence or an absence of an electrical breakdown in the first gate dielectric layer represents a binary logic state of the first memory cell.

公开(公告)号：US20220122681A1

公开(公告)日：2022-04-21

申请号：US17567705

申请日：2022-01-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： MENG-SHENG CHANG ,  YAO-JEN YANG ,  SHAO-YU CHOU ,  YIH WANG

IPC: G11C17/16 ,  G11C7/24 ,  G11C8/14 ,  G11C17/18 ,  G06F21/79 ,  G06F12/14

Abstract: A layout method includes: forming a layout structure of a memory array having first and second rows, each including a plurality of storage cells, wherein at least one of the storage cells includes a fuse; disposing a word line between the first and second rows; disposing a plurality of control electrodes across the word line for connecting the storage cells of the first row and the storage cells of the second row respectively; disposing a first cut layer on a first control electrode of the control electrodes located on a first side of the word line; and disposing a second cut layer on a second control electrode of the control electrodes located on a second side of the word line; wherein the first side of the word line is opposite to the second side of the word line.

公开(公告)号：US20210083065A1

公开(公告)日：2021-03-18

申请号：US16573803

申请日：2019-09-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： MENG-SHENG CHANG ,  CHIA-EN HUANG ,  YAO-JEN YANG ,  YIH WANG

IPC: H01L29/423 ,  G06F12/14

Abstract: A memory device includes a substrate, a semiconductor fin over the substrate and extending in a first direction, and a first gate electrode and a second gate electrode over the substrate and extending in a second direction. The semiconductor fin extends through the second gate electrode and terminates on the first gate electrode. The memory device further includes a first conductive via over and electrically coupled to the first gate electrode.

公开(公告)号：US20230114430A1

公开(公告)日：2023-04-13

申请号：US18066290

申请日：2022-12-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： MENG-SHENG CHANG ,  CHIA-EN HUANG ,  YAO-JEN YANG ,  YIH WANG

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/8234

Abstract: A memory device includes a substrate, a semiconductor fin over the substrate and extending in a first direction, a first gate electrode and a second gate electrode over the substrate and extending in a second direction, the semiconductor fin extending through the second gate electrode and terminating on the first gate electrode at one end of the semiconductor fin, and a first gate spacer and a second gate spacer laterally surrounding the first gate electrode and the second gate electrode, respectively. The one end of the semiconductor fin is surrounded by the first gate electrode. The first gate spacer includes a top substantially at a same height of a top of the second gate spacer.

公开(公告)号：US20210012846A1

公开(公告)日：2021-01-14

申请号：US16509524

申请日：2019-07-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： MENG-SHENG CHANG ,  YAO-JEN YANG ,  SHAO-YU CHOU ,  YIH WANG

IPC: G11C17/16 ,  G11C7/24 ,  G11C17/18 ,  G06F17/50 ,  G11C8/14

Abstract: A layout method includes: forming a layout structure of a memory array having a first row and a second row, wherein each of the first row and the second row comprises a plurality of storage cells; disposing a word line between the first row and the second row; disposing a plurality of control electrodes across the word line for connecting the plurality of storage cells of the first row and the plurality of storage cells of the second row respectively; disposing a first cut layer on a first control electrode of the plurality of control electrodes located on a first side of the word line; and disposing a second cut layer on a second control electrode of the plurality of control electrodes located on a second side of the word line; wherein the first side of the word line is opposite to the second side of the word line.

公开(公告)号：US20210257495A1

公开(公告)日：2021-08-19

申请号：US17232639

申请日：2021-04-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： MENG-SHENG CHANG ,  CHIA-EN HUANG ,  YAO-JEN YANG ,  YIH WANG

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/8239

Abstract: A memory device includes a substrate, a semiconductor fin over the substrate and extending in a first direction, and a first gate electrode and a second gate electrode over the substrate and extending in a second direction. The semiconductor fin extends through the second gate electrode and terminates on the first gate electrode at one end. The memory device further includes a first conductive via over and electrically coupled to the first gate electrode. The one end of the semiconductor fin is surrounded by the first gate electrode.

公开(公告)号：US20210104287A1

公开(公告)日：2021-04-08

申请号：US17123039

申请日：2020-12-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： MENG-SHENG CHANG ,  YAO-JEN YANG ,  SHAO-YU CHOU ,  YIH WANG

IPC: G11C17/16 ,  G11C7/24 ,  G11C8/14 ,  G11C17/18 ,  G06F21/79 ,  G06F12/14

Abstract: A layout method includes: forming a layout structure of a memory array having a first row, wherein the first row comprises a plurality of storage cells; disposing a word line; disposing a plurality of control electrodes for connecting the plurality of storage cells of the first row to the word line; and disposing a first cut layer on a first portion of a first control electrode of the plurality of control electrodes.