公开(公告)号：US20240147711A1

公开(公告)日：2024-05-02

申请号：US18404849

申请日：2024-01-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： PERNG-FEI YUH ,  YIH WANG ,  MENG-SHENG CHANG ,  JUI-CHE TSAI ,  KU-FENG LIN ,  YU-WEI LIN ,  KEH-JENG CHANG ,  CHANSYUN DAVID YANG ,  SHAO-TING WU ,  SHAO-YU CHOU ,  PHILEX MING-YAN FAN ,  YOSHITAKA YAMAUCHI ,  TZU-HSIEN YANG

IPC: H10B20/20 ,  G11C17/16 ,  G11C17/18

CPC classification number: H10B20/20 ,  G11C17/16 ,  G11C17/18

Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.

公开(公告)号：US20220342436A1

公开(公告)日：2022-10-27

申请号：US17238064

申请日：2021-04-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： PERNG-FEI YUH ,  YOSHITAKA YAMAUCHI ,  YIH WANG

IPC: G05F3/26

Abstract: The present disclosure provides a bias generating device and a method for generating bias. A bias generating device includes a first diode-connected transistor pair connected to receive a first voltage; a second diode-connected transistor pair connected to receive a second voltage; and a first transistor pair connected to the first diode-connected transistor pair and the second diode-connected transistor pair. The first transistor pair is configured to generate a third voltage in response to the first voltage and the second voltage.

公开(公告)号：US20220359484A1

公开(公告)日：2022-11-10

申请号：US17811903

申请日：2022-07-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： YI-CHING LIU ,  YIH WANG ,  CHIA-EN HUANG

IPC: H01L25/18 ,  G11C7/10 ,  G11C8/08 ,  H01L23/31 ,  H01L23/00 ,  G11C8/10

Abstract: A circuit is provided. The circuit includes a first die that includes a memory array, and the memory array includes a plurality of memory cells, a sensing element coupled to the plurality of memory cells, and a first plurality of conductive pads coupled to the sensing element. The circuit also includes a second die that includes an address decoder associated with the memory array of the first die and a second plurality of conductive pads coupled to the address decoder. The first die is coupled to the second die by an interposer. The address decoder of the second die is coupled to the sensing element of the first die. A first voltage swing of the first die is larger than a second voltage swing of the second die.

公开(公告)号：US20220122681A1

公开(公告)日：2022-04-21

申请号：US17567705

申请日：2022-01-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： MENG-SHENG CHANG ,  YAO-JEN YANG ,  SHAO-YU CHOU ,  YIH WANG

IPC: G11C17/16 ,  G11C7/24 ,  G11C8/14 ,  G11C17/18 ,  G06F21/79 ,  G06F12/14

Abstract: A layout method includes: forming a layout structure of a memory array having first and second rows, each including a plurality of storage cells, wherein at least one of the storage cells includes a fuse; disposing a word line between the first and second rows; disposing a plurality of control electrodes across the word line for connecting the storage cells of the first row and the storage cells of the second row respectively; disposing a first cut layer on a first control electrode of the control electrodes located on a first side of the word line; and disposing a second cut layer on a second control electrode of the control electrodes located on a second side of the word line; wherein the first side of the word line is opposite to the second side of the word line.

公开(公告)号：US20210083065A1

公开(公告)日：2021-03-18

申请号：US16573803

申请日：2019-09-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： MENG-SHENG CHANG ,  CHIA-EN HUANG ,  YAO-JEN YANG ,  YIH WANG

IPC: H01L29/423 ,  G06F12/14

Abstract: A memory device includes a substrate, a semiconductor fin over the substrate and extending in a first direction, and a first gate electrode and a second gate electrode over the substrate and extending in a second direction. The semiconductor fin extends through the second gate electrode and terminates on the first gate electrode. The memory device further includes a first conductive via over and electrically coupled to the first gate electrode.

公开(公告)号：US20240210983A1

公开(公告)日：2024-06-27

申请号：US18599233

申请日：2024-03-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： PERNG-FEI YUH ,  YOSHITAKA YAMAUCHI ,  YIH WANG

IPC: G05F3/26 ,  G05F3/24

CPC classification number: G05F3/262 ,  G05F3/24

Abstract: The present disclosure provides a bias generating device and a method for generating bias. A bias generating device includes a first diode-connected transistor pair connected to receive a first voltage; a second diode-connected transistor pair connected to receive a second voltage; and a first transistor pair connected to the first diode-connected transistor pair and the second diode-connected transistor pair. The first transistor pair is configured to generate a third voltage in response to the first voltage and the second voltage.

公开(公告)号：US20230114430A1

公开(公告)日：2023-04-13

申请号：US18066290

申请日：2022-12-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： MENG-SHENG CHANG ,  CHIA-EN HUANG ,  YAO-JEN YANG ,  YIH WANG

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/8234

Abstract: A memory device includes a substrate, a semiconductor fin over the substrate and extending in a first direction, a first gate electrode and a second gate electrode over the substrate and extending in a second direction, the semiconductor fin extending through the second gate electrode and terminating on the first gate electrode at one end of the semiconductor fin, and a first gate spacer and a second gate spacer laterally surrounding the first gate electrode and the second gate electrode, respectively. The one end of the semiconductor fin is surrounded by the first gate electrode. The first gate spacer includes a top substantially at a same height of a top of the second gate spacer.

公开(公告)号：US20210351193A1

公开(公告)日：2021-11-11

申请号：US17381090

申请日：2021-07-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： MENG-SHENG CHANG ,  CHIA-EN HUANG ,  YIH WANG

IPC: H01L27/112 ,  H01L23/525 ,  G11C17/18 ,  G11C17/16 ,  H01L23/528

Abstract: A method of forming a storage cell includes: forming a transistor on a semiconductor substrate; forming a plurality of fuses in at least one conductive layer on the semiconductor substrate to couple a connecting terminal of the transistor; forming a bit line to couple the plurality of fuses; and forming a word line to couple a control terminal of the transistor.

公开(公告)号：US20210012846A1

公开(公告)日：2021-01-14

申请号：US16509524

申请日：2019-07-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： MENG-SHENG CHANG ,  YAO-JEN YANG ,  SHAO-YU CHOU ,  YIH WANG

IPC: G11C17/16 ,  G11C7/24 ,  G11C17/18 ,  G06F17/50 ,  G11C8/14

Abstract: A layout method includes: forming a layout structure of a memory array having a first row and a second row, wherein each of the first row and the second row comprises a plurality of storage cells; disposing a word line between the first row and the second row; disposing a plurality of control electrodes across the word line for connecting the plurality of storage cells of the first row and the plurality of storage cells of the second row respectively; disposing a first cut layer on a first control electrode of the plurality of control electrodes located on a first side of the word line; and disposing a second cut layer on a second control electrode of the plurality of control electrodes located on a second side of the word line; wherein the first side of the word line is opposite to the second side of the word line.

公开(公告)号：US20230361100A1

公开(公告)日：2023-11-09

申请号：US18346856

申请日：2023-07-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： YI-CHING LIU ,  YIH WANG ,  CHIA-EN HUANG

IPC: H01L25/18 ,  H01L23/31 ,  H01L23/00 ,  G11C7/10 ,  G11C8/10 ,  G11C8/08

CPC classification number: H01L25/18 ,  H01L23/3157 ,  H01L24/24 ,  G11C7/1069 ,  G11C7/1096 ,  G11C8/10 ,  G11C8/08 ,  H01L2924/1434 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2924/1431

Abstract: A circuit is provided. The circuit includes a first die that includes a memory array, and the memory array includes a plurality of memory cells, a sensing element coupled to the plurality of memory cells, and a first plurality of conductive pads coupled to the sensing element. The circuit also includes a second die that includes an address decoder associated with the memory array of the first die and a second plurality of conductive pads coupled to the address decoder. The first die is coupled to the second die by an interposer. The address decoder of the second die is coupled to the sensing element of the first die. A first voltage swing of the first die is larger than a second voltage swing of the second die.