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    METHOD OF AND SYSTEM FOR MANUFACTURING SEMICONDUCTOR DEVICE
    1.
    发明申请
    METHOD OF AND SYSTEM FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220237358A1

    公开(公告)日：2022-07-28

    申请号：US17342295

    申请日：2021-06-08

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Yao-Jen YANG ,  Meng-Sheng CHANG

    IPC分类号： G06F30/392 ,  H01L27/02 ,  H01L27/118 ,  H01L27/12

    摘要： A method includes receiving a design rule deck including a predetermined set of widths and spacings associated with active regions. The method also includes providing a cell library including cells having respective active regions, wherein widths and spacings of the active regions are selected from the predetermined set of the design rule deck. The method includes placing a first cell and a second cell from the cell library in a design layout. The first cell has a cell height in a first direction, and a first active region having a first width in the first direction. The second cell has the cell height, and a second active region having a second width in the first direction. The second width is different from the first width. The method further includes manufacturing a semiconductor device according to the design layout.

    INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME
    2.
    发明公开
    INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME 审中-公开

    公开(公告)号：US20240268107A1

    公开(公告)日：2024-08-08

    申请号：US18165296

    申请日：2023-02-06

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Meng-Sheng CHANG ,  Yao-Jen YANG ,  Shao-Tung PENG ,  Chung-I HUANG

    IPC分类号： H10B20/25

    CPC分类号： H10B20/25

    摘要： An integrated circuit includes a first active region, a second active region, a first fuse and a dummy fuse. The first active region extends in a first direction, and is on a first level. The second active region extends in the first direction, is on the first level, and is separated from the first active region in a second direction different from the first direction. The first fuse extends in the first direction, is on a second level, overlaps the first active region and is electrically coupled to the first active region. The dummy fuse extends in the first direction, is on the second level, and is separated from the first fuse in the second direction. The dummy fuse overlaps the second active region, and is not electrically coupled to the second active region.

    MEMORY DEVICE AND MANUFACTURING METHOD AND TEST METHOD OF THE SAME
    3.
    发明公开
    MEMORY DEVICE AND MANUFACTURING METHOD AND TEST METHOD OF THE SAME 审中-公开

    公开(公告)号：US20240071442A1

    公开(公告)日：2024-02-29

    申请号：US17896506

    申请日：2022-08-26

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Min-Chiao YEH ,  Chieh LEE ,  Chia-En HUANG ,  Ji Kuan LEE ,  Yao-Jen YANG

    IPC分类号： G11C7/12 ,  G11C13/00

    CPC分类号： G11C7/12 ,  G11C13/0026 ,  G11C13/0028

    摘要： A method is provided, including following operations: activating a first word line to couple a first bit line with a second bit line to form a first conductive loop through a first transistor having a first terminal coupled to the first bit line and a second transistor having a first terminal coupled to the second bit line, wherein second terminals of the first and second transistors are coupled together; activating a second word line to couple a third bit line with a fourth bit line to form a second conductive loop, wherein the first and second word lines are disposed below the first to fourth bit lines; and identifying that the first conductive loop, the second conductive loop, or the combinations thereof is short-circuited or open-circuited.

    SEMICONDUCTOR DEVICE INCLUDING ANTI-FUSE CELL STRUCTURE
    5.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING ANTI-FUSE CELL STRUCTURE 审中-公开

    公开(公告)号：US20200058660A1

    公开(公告)日：2020-02-20

    申请号：US16533359

    申请日：2019-08-06

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    发明人： Meng-Sheng CHANG ,  Yao-Jen YANG

    IPC分类号： H01L27/112 ,  H01L23/528 ,  H01L23/525 ,  G11C17/18 ,  G06F17/50 ,  G11C17/16

    摘要： A structure includes a word line, a bit line, and an anti-fuse cell. The anti-fuse cell includes a reading device, a programming device, and a dummy device. The reading device includes a first gate coupled to the first word line, a first source/drain region coupled to the bit line, and a second source/drain region. The first source/drain region and the second source/drain region are on opposite sides of the first gate. The programming device includes a second gate, a third source/drain region coupled to the second source/drain region, and a fourth source/drain region. The third source/drain region and the fourth source/drain region are on opposite sides of the second gate. The dummy device includes a third gate, a fifth source/drain region coupled to the fourth source/drain region, and a sixth source/drain region. The fifth source/drain region and the sixth source/drain region are on opposite sides of the third gate.

    MEMORY DEVICE AND METHODS
    7.
    发明公开
    MEMORY DEVICE AND METHODS 审中-公开

    公开(公告)号：US20240331786A1

    公开(公告)日：2024-10-03

    申请号：US18741021

    申请日：2024-06-12

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Meng-Sheng CHANG ,  Yao-Jen YANG

    IPC分类号： G11C17/18 ,  G11C17/16 ,  H10B20/20

    CPC分类号： G11C17/18 ,  G11C17/16 ,  H10B20/20

    摘要： A memory device includes a bit line, a source line, a program word line, a read word line, a memory cell including a program transistor and a read transistor, and a controller. The program transistor includes a gate terminal coupled to the program word line, a first terminal coupled to the source line, and a second terminal. The read transistor includes a gate terminal coupled to the read word line, a first terminal coupled to the bit line, and a second terminal coupled to the second terminal of the program transistor. The controller is configured to, in a programming operation, cause a program current to flow through the memory cell along a first current path. The controller is further configured to, in a read operation, cause a read current to flow through the memory cell along a second current path different from the first current path.

    BIT CELL WITH BACK-SIDE METAL LINE DEVICE AND METHOD
    9.
    发明申请
    BIT CELL WITH BACK-SIDE METAL LINE DEVICE AND METHOD 有权

    公开(公告)号：US20230067140A1

    公开(公告)日：2023-03-02

    申请号：US17463172

    申请日：2021-08-31

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Chien-Ying CHEN ,  Yao-Jen YANG

    IPC分类号： H01L27/112 ,  G06F30/392

    摘要： A one-time programmable (OTP) bit cell includes a substrate including a front side and a back side, an active area on the front side, a first read transistor including a first gate and a first portion of the active area intersected by the first gate, a program transistor including a second gate and a second portion of the active area intersected by the second gate, a first electrical connection to the first gate, a second electrical connection to the second gate, and a third electrical connection to the active area. At least one of the first, second, or third electrical connections includes a metal line positioned on the back side.