利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

10 条记录 (耗时 0.018 秒)

    TEST CIRCUIT AND METHOD
    2.
    发明申请
    TEST CIRCUIT AND METHOD 有权

    公开(公告)号：US20210341535A1

    公开(公告)日：2021-11-04

    申请号：US17376338

    申请日：2021-07-15

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Hsieh-Hung HSIEH ,  Yen-Jen CHEN ,  Tzu-Jin YEH

    IPC分类号： G01R31/28

    摘要： A test circuit includes an oscillator configured to generate an oscillation signal, a device-under-test (DUT) configured to output an AC signal based on the oscillation signal, a first detection circuit configured to generate a first DC voltage having a first value based on the oscillation signal, and a second detection circuit configured to generate a second DC voltage having a second value based on the AC signal.

    PHASE FREQUENCY DETECTOR CIRCUIT
    4.
    发明申请
    PHASE FREQUENCY DETECTOR CIRCUIT 有权
    相位检测电路

    公开(公告)号：US20140103961A1

    公开(公告)日：2014-04-17

    申请号：US14133982

    申请日：2013-12-19

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Yen-Jen CHEN ,  I-Ting LEE ,  Feng Wei KUO ,  Huan-Neng CHEN ,  Chewn-Pu JOU

    IPC分类号： H03D13/00

    CPC分类号： H03D13/00 ,  H03D13/004 ,  H03L7/087 ,  H03L7/089 ,  H03L7/10

    摘要： A phase frequency detector circuit includes an edge detector circuit, a plurality of phase frequency detector sub-circuits, and a decision circuit. The edge detector circuit is configured to receive a first input signal and a second input signal. The decision circuit is configured to detect whether a blind condition exits based on outputs of the edge detector circuit and outputs of the plurality of phase frequency detector sub-circuits. Responsive to a result of the decision circuit, a corresponding frequency detector sub-circuit of the plurality of phase frequency detector sub-circuit is configured to provide signals for use in determining a phase difference between the first input signal and the second input signal.

    摘要翻译： 相位频率检测器电路包括边缘检测器电路，多个相位频率检测器子电路和判定电路。 边缘检测器电路被配置为接收第一输入信号和第二输入信号。 判定电路被配置为基于边缘检测器电路的输出和多个相位频率检测器子电路的输出来检测盲状态是否退出。 响应于判定电路的结果，多个相位频率检测器子电路的对应的频率检测器子电路被配置为提供用于确定第一输入信号和第二输入信号之间的相位差的信号。

    AUTO FREQUENCY CALIBRATION METHOD
    5.
    发明申请
    AUTO FREQUENCY CALIBRATION METHOD 有权
    自动频率校准方法

    公开(公告)号：US20170077932A1

    公开(公告)日：2017-03-16

    申请号：US15341183

    申请日：2016-11-02

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Yen-Jen CHEN ,  Feng Wei KUO ,  Huan-Neng CHEN ,  Chewn-Pu JOU

    IPC分类号： H03L7/08 ,  G04F10/00 ,  H03L7/10 ,  H03M3/00 ,  H03L7/093 ,  H03L7/099

    CPC分类号： H03L7/0802 ,  G04F10/005 ,  H03L7/085 ,  H03L7/093 ,  H03L7/0992 ,  H03L7/101 ,  H03L7/103 ,  H03L7/104 ,  H03L7/1976 ,  H03L2207/50 ,  H03M1/002 ,  H03M3/32

    摘要： A method of generating an output signal includes determining a sampling period N according to a number of most significant bits (MSBs) of a divider number control signal. The method also includes determining a first logic value of a control signal by a comparing circuit based on the sampling period N, and generating a coarse tuning signal by a code generating circuit based on a phase difference signal and the control signal. When an M-th least significant bit (LSB) of the number of MSBs of the divider number control signal equals a second logic value, the sampling period N is set based on the M-th LSB of the number of MSBs of the divider number control signal.

    摘要翻译： 产生输出信号的方法包括根据分频器号控制信号的最高有效位数（MSB）来确定采样周期N. 该方法还包括基于采样周期N由比较电路确定控制信号的第一逻辑值，并且基于相位差信号和控制信号通过代码产生电路产生粗调谐信号。 当除数编号控制信号的MSB的数量的第M个最低有效位（LSB）等于第二逻辑值时，采样周期N基于分频器数目的MSB的数量的第M个LSB来设置 控制信号。

    CIRCUIT AND OPERATING METHOD OF PLL
    6.
    发明申请
    CIRCUIT AND OPERATING METHOD OF PLL 有权
    PLL的电路和操作方法

    公开(公告)号：US20150162921A1

    公开(公告)日：2015-06-11

    申请号：US14097504

    申请日：2013-12-05

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Yen-Jen CHEN ,  Hsieh-Hung HSIEH ,  Chewn-Pu JOU ,  Fu-Lung HSUEH

    IPC分类号： H03L7/087

    CPC分类号： H03L7/087 ,  H03L7/0898

    摘要： A phase locked loop (PLL) includes a voltage controlled oscillator (VCO), a loop filter, and a feedback control unit. The VCO is configured to generate a first oscillating signal and a second oscillating signal according to a VCO control signal. The loop filter is configured to output the VCO control signal by low-pass filtering a signal at an input node of the loop filter. The feedback control unit has an output node coupled to the input node of the loop filter, the feedback control unit is configured to apply a first predetermined amount of current, along a first current direction, to the first feedback control output node during a variable period of time; and to apply one of K second predetermined amounts of current, along a second current direction opposite the first current direction, to the first feedback control output node during a predetermined period of time.

    摘要翻译： 锁相环（PLL）包括压控振荡器（VCO），环路滤波器和反馈控制单元。 VCO被配置为根据VCO控制信号产生第一振荡信号和第二振荡信号。 环路滤波器被配置为通过对环路滤波器的输入节点处的信号进行低通滤波来输出VCO控制信号。 所述反馈控制单元具有耦合到所述环路滤波器的输入节点的输出节点，所述反馈控制单元被配置为在可变周期期间沿着第一电流方向将第一预定量的电流施加到所述第一反馈控制输出节点 的时间 并且在预定时间段期间沿着与第一电流方向相反的第二电流方向将K个第二预定量的电流中的一个施加到第一反馈控制输出节点。

    AUTO FREQUENCY CALIBRATION FOR A PHASE LOCKED LOOP AND METHOD OF USE
    8.
    发明申请
    AUTO FREQUENCY CALIBRATION FOR A PHASE LOCKED LOOP AND METHOD OF USE 有权
    用于相位锁定环的自动频率校准及其使用方法

    公开(公告)号：US20150130518A1

    公开(公告)日：2015-05-14

    申请号：US14603900

    申请日：2015-01-23

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Yen-Jen CHEN ,  Feng Wei KUO ,  Huan-Neng CHEN ,  Chewn-Pu JOU

    IPC分类号： H03L7/08 ,  H03M1/00 ,  G04F10/00 ,  H03L7/099 ,  H03L7/085

    CPC分类号： H03L7/0802 ,  G04F10/005 ,  H03L7/085 ,  H03L7/093 ,  H03L7/0992 ,  H03L7/101 ,  H03L7/103 ,  H03L7/104 ,  H03L7/1976 ,  H03L2207/50 ,  H03M1/002 ,  H03M3/32

    摘要： An apparatus comprises a code generator configured to generate a coarse tuning signal and a reset signal based on a reference frequency and a phase difference signal. The apparatus also comprises a digital loop filter configured to generate a fine tuning signal based on the phase difference signal. The apparatus further comprises a voltage control oscillator configured to generate an output signal based on the coarse tuning signal and the fine tuning signal. The apparatus additionally comprises a divider configured to generate a divider frequency based on a divider control signal and the output signal. The phase difference signal is based, at least in part, on the divider frequency, and the divider is configured to be reset based on the reset signal.

    摘要翻译： 一种装置，包括代码发生器，其被配置为基于参考频率和相位差信号产生粗调谐信号和复位信号。 该装置还包括数字环路滤波器，其配置为基于相位差信号产生微调信号。 该装置还包括电压控制振荡器，被配置为基于粗调谐信号和微调信号产生输出信号。 该装置还包括分配器，其被配置为基于分频器控制信号和输出信号产生分频器频率。 相位差信号至少部分地基于分频器，并且分频器被配置为基于复位信号被复位。

    PHASE-LOCKED LOOPS THAT SHARE A LOOP FILTER AND FREQUENCY DIVIDER
    9.
    发明申请
    PHASE-LOCKED LOOPS THAT SHARE A LOOP FILTER AND FREQUENCY DIVIDER 有权
    分离环路滤波器和频率分路器的相位锁定

    公开(公告)号：US20140333355A1

    公开(公告)日：2014-11-13

    申请号：US14444385

    申请日：2014-07-28

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Feng Wei KUO ,  Shyh-An CHI ,  Huan-Neng CHEN ,  Yen-Jen CHEN ,  Chewn-Pu JOU

    IPC分类号： H03L7/07 ,  H03L7/099 ,  H03L7/093

    CPC分类号： H03L7/07 ,  H03L7/06 ,  H03L7/093 ,  H03L7/099

    摘要： A shared loop filter includes an input port configured to selectively receive a first input from a first charge pump. The first charge pump is connected to a first phase locked loop (PLL) in a first die. The input port is further configured to selectively receive a second input from a second charge pump, the second charge pump connected to a second PLL in a second die separate from the first die. The shared loop filter further includes an output port configured to selectively provide an output to a first voltage controlled oscillator (VCO). The first VCO is connected to the first PLL. The output port is further configured to selectively output a second output to a second VCO. The second VCO is connected to the second PLL.

    摘要翻译： 共享环路滤波器包括被配置为选择性地接收来自第一电荷泵的第一输入的输入端口。 第一电荷泵连接到第一芯片中的第一锁相环（PLL）。 所述输入端口还被配置为选择性地从第二电荷泵接收第二输入，所述第二电荷泵连接到与所述第一裸片分开的第二模具中的第二PLL。 共享环路滤波器还包括被配置为选择性地向第一压控振荡器（VCO）提供输出的输出端口。 第一个VCO连接到第一个PLL。 输出端口还被配置为选择性地将第二输出输出到第二VCO。 第二个VCO连接到第二个PLL。

    PHASE-LOCKED LOOPS THAT SHARE A LOOP FILTER
    10.
    发明申请
    PHASE-LOCKED LOOPS THAT SHARE A LOOP FILTER 有权
    分离循环过滤器的相位锁定

    公开(公告)号：US20140015576A1

    公开(公告)日：2014-01-16

    申请号：US14025125

    申请日：2013-09-12

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Feng Wei KUO ,  Shyh-An CHI ,  Huan-Neng CHEN ,  Yen-Jen CHEN ,  Chewn-Pu JOU

    IPC分类号： H03L7/06

    CPC分类号： H03L7/07 ,  H03L7/06 ,  H03L7/093 ,  H03L7/099

    摘要： An integrated circuit includes a first die and a second die. The first die comprising a first phase-locked loop (PLL) and the second die comprising a second PLL. The integrated circuit includes a shared loop filter, wherein the first PLL in the first die is combined with the shared loop filter to form a first PLL feedback loop, the second PLL in the second die is combined with the shared loop filter to form a second PLL feedback loop and the shared loop filter is configured to provide configurable bandwidths to each of the first PLL feedback loop and the second PLL feedback loop.

    摘要翻译： 集成电路包括第一管芯和第二管芯。 第一管芯包括第一锁相环（PLL），第二管芯包括第二PLL。 集成电路包括共享环路滤波器，其中第一管芯中的第一PLL与共享环路滤波器组合以形成第一PLL反馈环路，第二管芯中的第二PLL与共享环路滤波器组合以形成第二PLL PLL反馈环路和共享环路滤波器被配置为向第一PLL反馈环路和第二PLL反馈环路中的每一个提供可配置带宽。