公开(公告)号：US12092301B2

公开(公告)日：2024-09-17

申请号：US16968152

申请日：2019-02-08

Applicant: SIGNIFY HOLDING B.V.

Inventor： Rifat Ata Mustafa Hikmet ,  Ties Van Bommel

IPC: F21V23/00 ,  H05K1/02 ,  F21K9/00 ,  F21K9/90 ,  F21Y115/10

CPC classification number: F21V23/005 ,  H05K1/0203 ,  F21K9/00 ,  F21K9/90 ,  F21Y2115/10 ,  H05K2201/099 ,  H05K2201/10106

Abstract: A lighting arrangement (10) is disclosed, comprising a substrate (11) for mechanically and electrically connecting at least one light-emitting element (12) thereto. The substrate (11) comprises at least a first side (13) and a second side (14), and a circumferential edge (20) along a periphery of the substrate, the circumferential edge (20) extending between the first side (13) and the second side (14), and at least one electrically conductive region (16) disposed on the first side (13). The lighting arrangement (10) comprises at least one thermally conductive element (18) arranged such that the at least one thermally conductive element (18) is coupled to at least a portion of the second side (14) and to at least a portion of an outer surface (17) of the circumferential edge (20), and such that the at least one thermally conductive element (18) is not coupled to the at least one electrically conducting region (16).

公开(公告)号：US20240215159A1

公开(公告)日：2024-06-27

申请号：US18131019

申请日：2023-04-05

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Sang-min Lee ,  Youngil Cho

IPC: H05K1/03 ,  H05K1/11 ,  H05K3/00 ,  H05K3/10

CPC classification number: H05K1/0353 ,  H05K1/111 ,  H05K1/115 ,  H05K3/0017 ,  H05K3/103 ,  H05K2201/0939 ,  H05K2201/099

Abstract: A circuit board according to an embodiment includes: a first insulating layer that does not include a reinforcing material; a conductive pad that protrudes above a surface of the first insulating layer, and a second insulating layer that is disposed below the first insulating layer and includes a reinforcing material. A corner of the conductive pad has a curved shape.

公开(公告)号：US20240032188A1

公开(公告)日：2024-01-25

申请号：US18298667

申请日：2023-04-11

Applicant: Samsung Electronics Co.,Ltd.

Inventor： Sun Jun KIM

IPC: H05K1/02 ,  H05K1/14

CPC classification number: H05K1/0269 ,  H05K1/142 ,  H05K2201/099

Abstract: A substrate including a base substrate and first to fourth identification codes on the base substrate, wherein the substrate is one of a plurality of substrates at a row ‘c’ and a column ‘d’ in a (b)th strip of an (a)th panel, where ‘a’, ‘b’, ‘c’ and ‘d’ are natural numbers, the plurality of substrates being included in the (b)th strip of the (a)th panel, the first identification code includes information on the ‘a’, the second identification code includes information on the ‘b’, the third identification code includes information on the ‘c’, and the fourth identification code includes information on the ‘d’, may be provided.

公开(公告)号：US20230337370A1

公开(公告)日：2023-10-19

申请号：US18337706

申请日：2023-06-20

Applicant: LG INNOTEK CO., LTD.

Inventor： Yun Mi BAE ,  Soon Gyu KWON ,  Sang Hwa KIM ,  Sang Young LEE ,  Jin Hak LEE ,  Han Su LEE ,  Dong Hun JEONG ,  In Ho JEONG ,  Dae Young CHOI ,  Jung Ho HWANG

IPC: H05K3/24 ,  H05K3/10 ,  C25D5/48 ,  H05K3/18 ,  H05K1/09 ,  C25D7/12 ,  H05K1/02 ,  C25D3/48 ,  C25D5/02 ,  H05K1/11 ,  C25D3/38

CPC classification number: H05K3/244 ,  H05K3/108 ,  C25D5/48 ,  H05K3/181 ,  H05K1/09 ,  C25D7/123 ,  H05K1/0296 ,  C25D3/48 ,  H05K3/188 ,  C25D5/022 ,  H05K1/11 ,  H05K2201/0989 ,  C25D3/38 ,  H05K2201/0338 ,  H05K2201/099 ,  H05K2201/098 ,  H05K2203/1184

Abstract: A printed circuit board includes an insulating layer, a circuit pattern on the insulating layer, and a surface treatment layer on the circuit pattern. The surface treatment layer includes a bottom surface having a width wider than a width of a top surface of the circuit pattern.

公开(公告)号：US20190244886A1

公开(公告)日：2019-08-08

申请号：US16385285

申请日：2019-04-16

Applicant: DENSO CORPORATION

Inventor： Kosuke SUZUKI ,  Atsushi KASHIWAZAKI ,  Yuki SANADA ,  Toshihiro NAKAMURA ,  Shinya UCHIBORI

IPC: H01L23/498 ,  H05K1/11

CPC classification number: H01L23/49838 ,  H01L23/28 ,  H01L23/31 ,  H01L23/49827 ,  H05K1/114 ,  H05K3/28 ,  H05K2201/09236 ,  H05K2201/0989 ,  H05K2201/099

Abstract: A solder resist is configured such that pattern covering portions of the solder resist covering straight portions of adjacent wiring patterns are separated from each other in an area outside of a resin mold part. Thus, even if the solder resist is cracked, cracks will not be formed so as to connect between the adjacent wiring patterns. As such, even if moisture generated by condensation or the like enters in the crack, it is less likely that a short circuit will occur between the adjacent wiring patterns.

公开(公告)号：US20190124767A1

公开(公告)日：2019-04-25

申请号：US16169340

申请日：2018-10-24

Applicant: IBIDEN CO., LTD.

Inventor： Takema ADACHI ,  Toshihide MAKINO ,  Hidetoshi NOGUCHI

IPC: H05K1/11 ,  H05K3/46 ,  H05K1/03 ,  H05K3/06 ,  H05K3/42

CPC classification number: H05K1/115 ,  H05K1/0373 ,  H05K3/06 ,  H05K3/422 ,  H05K3/4644 ,  H05K3/4652 ,  H05K2201/09227 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09727 ,  H05K2201/09827 ,  H05K2201/099 ,  H05K2203/072 ,  H05K2203/107 ,  H05K2203/1572

Abstract: A printed wiring board includes: a core substrate having a core layer, first and second conductor layers, and through-hole conductors penetrating through the core layer and connecting the conductor layers; and first and second build-up layers each including an insulating layer, an inner side conductor layer, an outermost insulating layer, an outermost conductor layer, and a solder resist layer. Each of the conductor layers includes conductor circuits having substantially a trapezoid cross-sectional shape, and spaces between adjacent conductor circuits, and includes a metal foil, a seed layer, and an electrolytic plating film. The inner side conductor layers have the smallest minimum circuit width, the smallest minimum space width and the largest base angle among the conductor layers. The insulating layers have the smallest ten-point average roughness rz3, rz7 among the ten-point average roughness rz3, rz7, rz1, rz2, rz5 and rz9 of the core layer, insulating layers and outermost insulating layers.

公开(公告)号：US09961764B2

公开(公告)日：2018-05-01

申请号：US14069402

申请日：2013-11-01

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Hiromichi Kitajima

IPC: H05K1/00 ,  H05K1/02 ,  H01L23/498 ,  H05K1/11 ,  H05K1/18 ,  H05K7/06 ,  H05K3/46

CPC classification number: H05K1/0271 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K1/113 ,  H05K1/181 ,  H05K3/4629 ,  H05K7/06 ,  H05K2201/09381 ,  H05K2201/0979 ,  H05K2201/099 ,  H01L2924/00

Abstract: A via conductor connected to a mounting electrode near a corner portion of a circuit substrate is provided in a position in a corresponding mounting electrode, located closer to the center of the circuit substrate. Thus, concentration of a stress in a portion of the via conductor is effectively reduced, and a break, a chip, or a crack is prevented from occurring to the circuit substrate. Even if the portion located closer to the corner portion of the mounting electrode is peeled from the circuit substrate, the electrical characteristics of the circuit module are secured because disconnection between the corresponding mounting electrode and the via conductor is prevented.

公开(公告)号：US09913383B2

公开(公告)日：2018-03-06

申请号：US15594778

申请日：2017-05-15

Applicant: LG INNOTEK CO., LTD.

Inventor： Yun Mi Bae ,  Soon Gyu Kwon ,  Sang Hwa Kim ,  Sang Young Lee ,  Jin Hak Lee ,  Han Su Lee ,  Dong Hun Jeong ,  In Ho Jeong ,  Dae Young Choi ,  Jung Ho Hwang

IPC: H05K1/09 ,  H05K3/24 ,  H05K3/18 ,  C25D5/48 ,  C25D5/02 ,  C25D3/38 ,  C25D3/48 ,  C25D7/12

CPC classification number: H05K1/11 ,  C25D3/38 ,  C25D3/48 ,  C25D5/022 ,  C25D5/48 ,  C25D7/123 ,  H05K1/09 ,  H05K3/108 ,  H05K3/181 ,  H05K3/188 ,  H05K3/244 ,  H05K2201/0338 ,  H05K2201/098 ,  H05K2201/0989 ,  H05K2201/099 ,  H05K2203/1184

Abstract: A printed circuit board includes: an insulating layer; a plating seed layer disposed on the insulating layer; a circuit pattern layer disposed on the plating seed layer and formed of copper (Cu); and a surface treatment layer disposed on the circuit pattern layer and formed of gold (Au), wherein a width of a bottom surface of the surface treatment layer is narrower than a width of a top surface of the plating seed layer, wherein the bottom surface of the surface treatment layer includes: a first portion contacted with the circuit pattern layer; and a second portion non contacted with the circuit pattern layer, and wherein a width of a top surface of the circuit pattern layer is narrower than a width of a bottom surface of the circuit pattern layer.

公开(公告)号：US09681544B2

公开(公告)日：2017-06-13

申请号：US15070659

申请日：2016-03-15

Applicant: FUJITSU LIMITED

Inventor： Takahiro Kitagawa

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/111 ,  H05K1/0216 ,  H05K2201/09272 ,  H05K2201/099 ,  H05K2201/10371 ,  Y02P70/611

Abstract: A printed substrate includes: a substrate; a copper layer formed on the substrate; and a resin formed on the substrate to cover a part of the copper layer, wherein the copper layer includes a first region covered by the resin and a second region in which a shield sheet metal is installed, the shield sheet metal surrounding a predetermined region of the substrate, and wherein an angle formed between an outer edge portion of the copper layer covered by the resin and an outer edge portion of the resin which covers the copper layer at a location at which the outer edge portion of the copper layer and the outer edge portion of the resin intersect each other as viewed in plan is an obtuse angle.

公开(公告)号：US20170055342A1

公开(公告)日：2017-02-23

申请号：US14832462

申请日：2015-08-21

Applicant: The Boeing Company

Inventor： Tai Anh Lam ,  Jean Ann Nielsen ,  Minas H. Tanielian

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/12 ,  H05K3/40 ,  H05K3/04 ,  H05K3/06 ,  H05K1/18 ,  H05K3/30

CPC classification number: H05K1/141 ,  H05K2201/041 ,  H05K2201/09563 ,  H05K2201/099 ,  H05K2201/10098 ,  H05K2201/10166

Abstract: A microwave device can include a printed circuit board substrate having a first microwave device subcircuit and a microdevice substrate having a second microwave device subcircuit. The first microwave device subcircuit may be formed at a low resolution and a low tolerance, while the second microwave device subcircuit may be formed at a high resolution and a high tolerance. The first microwave device subcircuit and the second microwave device subcircuit may be electrically coupled using a conductor.

Abstract translation: 微波装置可以包括具有第一微波装置分支电路的印刷电路板基板和具有第二微波装置子电路的微装置基板。 第一微波器件子电路可以以低分辨率和低容差形成，而第二微波器件子电路可以以高分辨率和高容差形成。 第一微波器件子电路和第二微波器件子电路可以使用导体电耦合。