公开(公告)号：US20240145432A1

公开(公告)日：2024-05-02

申请号：US18549307

申请日：2022-03-01

Applicant: TESLA, INC.

Inventor： Mengzhi Pang ,  Yang Sun ,  Yong guo Li ,  Jianjun Li ,  Rodrigo Rodriguez Navarrete ,  Vijaykumar Krithivasan ,  Rishabh Bhandari

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/367 ,  H01L23/552 ,  H01L23/60

CPC classification number: H01L25/0652 ,  H01L23/3672 ,  H01L23/552 ,  H01L23/60 ,  H01L24/48 ,  H01L24/16 ,  H01L2224/16221 ,  H01L2224/48245

Abstract: The present disclosure relates to processing systems and more specifically to integrated circuit (IC) packages designed to reduce the effects of electrostatic discharge and/or electromagnetic interference during integrated circuit manufacture and/or use. The IC assembly may include a wafer positioned between a cooling system and thermal dissipation structure. The cooling system and thermal dissipation structure include electrically conductive material at a ground potential such that the thermal systems act as electrical ground. The wafer may be electrically connected to the cooling system and thermal dissipation structure to reduce static charge accumulation during the assembly process. The cooling system and thermal dissipation structure may further provide radio frequency (RF) shielding to reduce electromagnetic interference during use of the IC assembly.

公开(公告)号：US11122678B2

公开(公告)日：2021-09-14

申请号：US16735573

申请日：2020-01-06

Applicant: Tesla, Inc.

Inventor： Vijaykumar Krithivasan ,  Jin Zhao ,  Mengzhi Pang ,  Steven Wayne Butler ,  Ganesh Venkataramanan ,  Yang Sun

IPC: H05K1/02 ,  H01L23/00 ,  H05K3/30

Abstract: A structure having imbedded array of components is described. An example structure includes an imbedded component array layer having an array of imbedded passive devices contained therein. The structure further includes an Integrated Fan-Out (InFO) layer residing adjacent a first surface of the imbedded component array layer having traces and vias formed therein. The structure further includes an insulator layer residing adjacent a second surface of the imbedded component array layer and electrically coupled to at least the InFO layer and vias passing through the imbedded component array layer and electrically coupled to some of vias of the InFO layer.

公开(公告)号：US20200221568A1

公开(公告)日：2020-07-09

申请号：US16735573

申请日：2020-01-06

Applicant: Tesla, Inc.

Inventor： Jin Zhao ,  Vijaykumar Krithivasan ,  Mengzhi Pang ,  Steven Wayne Butler ,  Ganesh Venkataramanan ,  Yang Sun

IPC: H05K1/02 ,  H05K3/30 ,  H01L23/00

Abstract: A structure having embedded array of components is described. An example structure includes an imbedded component array layer having an array of imbedded passive devices contained therein. The structure further includes an Integrated Fan-Out (InFO) layer residing adjacent a first surface of the imbedded component array layer having traces and vias formed therein. The structure further includes an insulator layer residing adjacent a second surf ace of the imbedded component array layer and electrically coupled to at least the InFO layer and vias passing through the imbedded component array layer and electrically coupled to some of vias of the InFO layer.

公开(公告)号：US20240370070A1

公开(公告)日：2024-11-07

申请号：US18683342

申请日：2022-08-15

Applicant: Tesla, Inc.

Inventor： Jin Zhao ,  Shishuang Sun ,  Yang Sun ,  Vijaykumar Krithivasan ,  William Chang ,  Jianjun Li

IPC: G06F1/26

Abstract: Aspects of this disclosure relate to power delivery to chips in an array. An array of power conversion paths can be positioned vertically relative to the chips of the array. A power conversion path can convert a high voltage, low current signal to a low voltage, high current. The power conversion path can include a first power conversion stage and a second power conversion stage. The power conversion path can be implemented in a power supply module, for example.

公开(公告)号：US20240357769A1

公开(公告)日：2024-10-24

申请号：US18683408

申请日：2022-08-16

Applicant: Tesla, Inc.

Inventor： Shishuang Sun ,  Ganesh Venkataramanan ,  Yang Sun ,  Jin Zhao ,  Shaowei Deng ,  William Chang ,  Mengzhi Pang ,  Steven Butler ,  William Arthur McGee ,  Aydin Nabovati

IPC: H05K7/20

CPC classification number: H05K7/205

Abstract: The systems, methods, and devices disclosed herein relate to a multi-layer structures arranged in a vertically orientation. In some embodiments, a computing assembly can include a first cooling system, a first electronics layer, a second cooling system, and a second electronics layer. The first cooling system can be disposed on top of and can be in thermal communication with the first electronics layer. The first electronics layer array includes an array of integrated circuit dies that are in electronic communication with each other in a plane that is orthogonal to power delivery. The first electronics layer can be disposed on top of and can be in thermal communication with the second cooling system, and the second cooling system can be disposed on top of and can be in thermal communication with the second electronics layer. The second electronics layer includes an array of power delivery modules. In some embodiments, at least one layer can use system on wafer packaging.