公开(公告)号：US11367680B2

公开(公告)日：2022-06-21

申请号：US16766616

申请日：2018-11-30

Applicant: Tesla, Inc.

Inventor： Mengzhi Pang ,  Shishuang Sun ,  Ganesh Venkataramanan

IPC: H01L23/522 ,  H01L25/065 ,  H01L23/36 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538

Abstract: An electronic assembly (100) includes a mechanical carrier (102), a plurality of integrated circuits (104A, 104B) disposed on the mechanical carrier, a fan out package (108) disposed on the plurality of integrated circuits, a plurality of singulated substrates (112A, 112B) disposed on the fan out package, a plurality of electronic components (114A, 114B) disposed on the plurality of singulated substrates, and at least one stiffness ring (116A, 116B, 116C) disposed on the plurality of singulated substrates. A method for constructing an electronic assembly includes identifying a group of known good singulated substrates, joining the group of known good singulated substrates into a substrate panel, attaching at least one bridge to the substrate panel that electrically couples at least two of the known good singulated substrates, and mounting a plurality of electronic components onto the substrate panel, each electronic component of the plurality of electronic components corresponding to a respective known good singulated substrate.

公开(公告)号：US20240353905A1

公开(公告)日：2024-10-24

申请号：US18683469

申请日：2022-08-15

Applicant: Tesla, Inc.

Inventor： Jin Zhao ,  Raghuvir Ramachandran ,  Shishuang Sun ,  William Chang ,  Timothy Fischer

IPC: G06F1/26

CPC classification number: G06F1/26

Abstract: Systems and methods of for vertical power and clock delivery are disclosed. In some embodiments, a computing system can include an array of chips comprising a chip and a power delivery module configured to provide a power supply voltage and one or more clock signals to the chip, the power delivery module being positioned vertically relative to the chip, and the chip configured to vertically receive the one or more clock signals from the power delivery module.

公开(公告)号：US11901310B2

公开(公告)日：2024-02-13

申请号：US17276071

申请日：2019-09-19

Applicant: Tesla, Inc.

Inventor： Mengzhi Pang ,  Shishuang Sun ,  Ganesh Venkataramanan ,  William Arthur McGee ,  Steven Butler

IPC: H01L23/34 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/32 ,  H01L23/538

CPC classification number: H01L23/562 ,  H01L25/0652 ,  H01L25/18 ,  H01L23/32 ,  H01L23/5386

Abstract: An electronic assembly includes a substrate having a first surface and a second surface opposite to the first surface and a plurality of stiffening members coupled to the substrate. The substrate further includes a plurality of substrate interconnects. The electronic assembly further includes a plurality of semiconductor dies mounted on the first surface of the substrate. The plurality of semiconductor dies are electrically connected to each other via the plurality of substrate interconnects. The electronic assembly further includes a plurality of power supply modules mounted on the second surface of the substrate. Each power supply module is disposed opposite to a respective semiconductor die.

公开(公告)号：US20210351104A1

公开(公告)日：2021-11-11

申请号：US17277893

申请日：2019-09-19

Applicant: Tesla, Inc.

Inventor： Robert Yinan Cao ,  Mitchell Heschke ,  Mengzhi Pang ,  Shishuang Sun ,  Vijaykumar Krithivasan

IPC: H01L23/40 ,  H01L25/065 ,  H01L23/498 ,  H01L25/00

Abstract: Described is a multi-chip module that may include a Redistribution Layer (RDL) substrate having Integrated Circuit (IC) dies mounted to a first surface of the RDL substrate. A second plurality of IC dies may be mounted to an opposite second surface. A plurality of sockets can be mounted upon the second plurality of IC dies and a cold plate then mounted to the first plurality of IC dies. The mounting structure may include socket frames coupled to the plurality of sockets.

公开(公告)号：US11973004B2

公开(公告)日：2024-04-30

申请号：US17277893

申请日：2019-09-19

Applicant: Tesla, Inc.

Inventor： Robert Yinan Cao ,  Mitchell Heschke ,  Mengzhi Pang ,  Shishuang Sun ,  Vijaykumar Krithivasan

IPC: H01L23/40 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/4006 ,  H01L23/49822 ,  H01L23/49838 ,  H01L25/0652 ,  H01L25/50 ,  H01L2023/4081 ,  H01L2023/4087

Abstract: Described is a multi-chip module that may include a Redistribution Layer (RDL) substrate having Integrated Circuit (IC) dies mounted to a first surface of the RDL substrate. A second plurality of IC dies may be mounted to an opposite second surface. A plurality of sockets can be mounted upon the second plurality of IC dies and a cold plate then mounted to the first plurality of IC dies. The mounting structure may include socket frames coupled to the plurality of sockets.

公开(公告)号：US11894770B2

公开(公告)日：2024-02-06

申请号：US16762481

申请日：2018-11-07

Applicant: Tesla, Inc.

Inventor： Shishuang Sun ,  Kevin Hurd ,  Satyan Chandra

IPC: H02M3/156 ,  G06F1/20 ,  G06F1/26 ,  H02M1/12 ,  H02M7/00

CPC classification number: H02M3/156 ,  G06F1/20 ,  G06F1/26 ,  H02M1/126 ,  H02M7/003 ,  G06F2200/201

Abstract: A Voltage Regulator Module (VRM) includes a first voltage rail circuit board oriented in a first plane having formed therein a first plurality of conductors and configured to produce a first rail voltage, a second voltage rail circuit board oriented in a second plane that is substantially parallel to the first plane having formed therein a second plurality of conductors and configured to produce a second rail voltage. The VRM also includes a first capacitor circuit board oriented in a third plane that is substantially perpendicular to the first plane and a second capacitor circuit board oriented in a fourth plane that is substantially parallel to the third plane. The VRM includes a plurality of conductors intercoupling the first voltage rail circuit board, the first capacitor circuit board, the second voltage rail circuit board, and the second capacitor circuit board.

公开(公告)号：US20240015887A1

公开(公告)日：2024-01-11

申请号：US18255853

申请日：2021-12-14

Applicant: Tesla, Inc.

Inventor： Jin Zhao ,  Satyan Chandra ,  Shishuang Sun

IPC: H05K1/11 ,  H05K3/34 ,  H05K3/32

CPC classification number: H05K1/113 ,  H05K3/3436 ,  H05K3/3442 ,  H05K3/328 ,  H05K2201/10636 ,  H05K2201/10734 ,  H05K2201/10015 ,  H05K2203/101 ,  H05K2203/107

Abstract: A structure with an electronic component array positioned between two stacked printed circuit boards (600,606) is disclosed. The electronic components (502) of the array can be connected to the printed circuit board (600,606) by way of solder connections. Example electronic components (502) include capacitors. Related methods of manufacture are disclosed that involve applying heat to a solder paste array on a printed circuit board (600,606) to form solid conductors electrically connected to the electronic components (502).

公开(公告)号：US20220392836A1

公开(公告)日：2022-12-08

申请号：US17807475

申请日：2022-06-17

Applicant: Tesla, Inc.

Inventor： Mengzhi Pang ,  Shishuang Sun ,  Ganesh Venkataramanan

IPC: H01L23/522 ,  H01L21/48 ,  H01L23/36 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

Abstract: An electronic assembly includes a mechanical carrier, a plurality of integrated circuits disposed on the mechanical carrier, a fan out package disposed on the plurality of integrated circuits, a plurality of singulated substrates disposed on the fan out package, a plurality of electronic components disposed on the plurality of singulated substrates, and at least one stiffness ring disposed on the plurality of singulated substrates. A method for constructing an electronic assembly includes identifying a group of known good singulated substrates, joining the group of known good singulated substrates into a substrate panel, attaching at least one bridge to the substrate panel that electrically couples at least two of the known good singulated substrates, and mounting a plurality of electronic components onto the substrate panel, each electronic component of the plurality of electronic components corresponding to a respective known good singulated substrate.

公开(公告)号：US20240370070A1

公开(公告)日：2024-11-07

申请号：US18683342

申请日：2022-08-15

Applicant: Tesla, Inc.

Inventor： Jin Zhao ,  Shishuang Sun ,  Yang Sun ,  Vijaykumar Krithivasan ,  William Chang ,  Jianjun Li

IPC: G06F1/26

Abstract: Aspects of this disclosure relate to power delivery to chips in an array. An array of power conversion paths can be positioned vertically relative to the chips of the array. A power conversion path can convert a high voltage, low current signal to a low voltage, high current. The power conversion path can include a first power conversion stage and a second power conversion stage. The power conversion path can be implemented in a power supply module, for example.

公开(公告)号：US20240357769A1

公开(公告)日：2024-10-24

申请号：US18683408

申请日：2022-08-16

Applicant: Tesla, Inc.

Inventor： Shishuang Sun ,  Ganesh Venkataramanan ,  Yang Sun ,  Jin Zhao ,  Shaowei Deng ,  William Chang ,  Mengzhi Pang ,  Steven Butler ,  William Arthur McGee ,  Aydin Nabovati

IPC: H05K7/20

CPC classification number: H05K7/205

Abstract: The systems, methods, and devices disclosed herein relate to a multi-layer structures arranged in a vertically orientation. In some embodiments, a computing assembly can include a first cooling system, a first electronics layer, a second cooling system, and a second electronics layer. The first cooling system can be disposed on top of and can be in thermal communication with the first electronics layer. The first electronics layer array includes an array of integrated circuit dies that are in electronic communication with each other in a plane that is orthogonal to power delivery. The first electronics layer can be disposed on top of and can be in thermal communication with the second cooling system, and the second cooling system can be disposed on top of and can be in thermal communication with the second electronics layer. The second electronics layer includes an array of power delivery modules. In some embodiments, at least one layer can use system on wafer packaging.