公开(公告)号：US12235319B2

公开(公告)日：2025-02-25

申请号：US18520797

申请日：2023-11-28

Applicant: Texas Instruments Incorporated

Inventor： Abhinay Patil ,  Kavitha Balaramaiah ,  Mahadev Gopalakrishnan

IPC: G01R31/3177 ,  G01R31/28 ,  G01R31/3183 ,  G01R31/327 ,  G06F13/16

Abstract: Described embodiments include a fault monitoring system comprising a fault logic circuit having a fault logic input adaptable to be coupled to sensor inputs, and first and second fault logic outputs. The fault logic circuit compares a plurality of data values provided by respective sensor inputs to respective fault thresholds, and provides respective fault signals at the first fault logic output responsive to a fault event in which a respective data value exceeds its respective fault threshold. A timer has a timer input coupled to the reset output, and a timer output. A data register has a first data register input coupled to the write control output, a second data register input coupled to the timer output, and a data register output. The data register receives fault data that includes an event identifier, a timer value, and a timer expiration indicator.

公开(公告)号：US20240393392A1

公开(公告)日：2024-11-28

申请号：US18520797

申请日：2023-11-28

Applicant: Texas Instruments Incorporated

Inventor： Abhinay Patil ,  Kavitha Balaramaiah ,  Mahadev Gopalakrishnan

IPC: G01R31/3177 ,  G06F13/16

Abstract: Described embodiments include a fault monitoring system comprising a fault logic circuit having a fault logic input adaptable to be coupled to sensor inputs, and first and second fault logic outputs. The fault logic circuit compares a plurality of data values provided by respective sensor inputs to respective fault thresholds, and provides respective fault signals at the first fault logic output responsive to a fault event in which a respective data value exceeds its respective fault threshold. A timer has a timer input coupled to the reset output, and a timer output. A data register has a first data register input coupled to the write control output, a second data register input coupled to the timer output, and a data register output. The data register receives fault data that includes an event identifier, a timer value, and a timer expiration indicator.

公开(公告)号：US20250164554A1

公开(公告)日：2025-05-22

申请号：US19024722

申请日：2025-01-16

Applicant: Texas Instruments Incorporated

Inventor： Abhinay Patil ,  Kavitha Balaramaiah ,  Mahadev Gopalakrishnan

IPC: G01R31/3177 ,  G01R31/28 ,  G01R31/3183 ,  G01R31/327 ,  G06F13/16

Abstract: Described embodiments include a fault monitoring system comprising a fault logic circuit having a fault logic input adaptable to be coupled to sensor inputs, and first and second fault logic outputs. The fault logic circuit compares a plurality of data values provided by respective sensor inputs to respective fault thresholds, and provides respective fault signals at the first fault logic output responsive to a fault event in which a respective data value exceeds its respective fault threshold. A timer has a timer input coupled to the reset output, and a timer output. A data register has a first data register input coupled to the write control output, a second data register input coupled to the timer output, and a data register output. The data register receives fault data that includes an event identifier, a timer value, and a timer expiration indicator.

公开(公告)号：US10541525B1

公开(公告)日：2020-01-21

申请号：US16287458

申请日：2019-02-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhrarup Barman Roy ,  Abhishek Kumar ,  Subrato Roy ,  Ankur Chauhan ,  Abhinay Patil

IPC: G06F13/20 ,  G06F13/24 ,  H02H3/06 ,  H03K5/135 ,  H03K21/10 ,  H03K21/38 ,  H03K19/20

Abstract: The present disclosure relates to configuring parameters of a system. In some examples, a timer duration circuit can be configured to output a timer duration signal defining a time duration for a retry signal based on an impedance of a first circuit coupled at a first node. A logic circuit can be configured to control an output of the retry signal to at least one integrator circuit to control a current to a second node based on one of the timer duration signal and a retry timer signal, and a combination thereof. An output circuit can be configured to output a stop retry signal based on a voltage established by a second circuit at the second node based on its impedance and the current. The stop retry signal can indicate a number of retries that have occurred and can be based on the capacitances of the first and second circuits.