公开(公告)号：US11977407B2

公开(公告)日：2024-05-07

申请号：US17683185

申请日：2022-02-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Apoorva Bhatia ,  Pranav Kumar ,  Abhrarup Barman Roy ,  Peeyoosh Mirajkar ,  Raghavendra Reddy

IPC: G06F1/12 ,  G06F1/08 ,  H03K3/037 ,  H03K19/20

CPC classification number: G06F1/12 ,  G06F1/08 ,  H03K3/037 ,  H03K19/20

Abstract: In an example, a system is adapted to be coupled to a load device having a load clock. The system includes a clock generation device with a pin. The system also includes a capture circuit coupled to the pin and operable to sample a value at the pin. The system includes a D flip-flop having a data input coupled to the capture circuit, a clock input coupled to a clock, and having an output, where the D flip-flop is operable to provide, at the output, a system reference event (SYSREF) signal to align the load clock to the clock, based at least in part on the value at the pin.

公开(公告)号：US11184015B2

公开(公告)日：2021-11-23

申请号：US15873758

申请日：2018-01-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ankur Chauhan ,  Abhrarup Barman Roy

IPC: H03L7/183 ,  H03K5/1252 ,  H03K5/24 ,  H03K17/041 ,  H03M1/46 ,  H03K17/693 ,  H03K19/0185 ,  H03M1/74 ,  H03K17/62

Abstract: In some examples, a device comprises a first driver coupled to a first node, the first node to couple to a first load external to the device. The device comprises a second driver coupled to a second node, the second node coupled to a second load internal to the device. The device comprises a comparison circuit having an inverting input coupled to the first node and a non-inverting input coupled to the second node. Sizes of the second driver and the second load are configured proportionately to sizes of the first driver and the first load, respectively.

公开(公告)号：US10541525B1

公开(公告)日：2020-01-21

申请号：US16287458

申请日：2019-02-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhrarup Barman Roy ,  Abhishek Kumar ,  Subrato Roy ,  Ankur Chauhan ,  Abhinay Patil

IPC: G06F13/20 ,  G06F13/24 ,  H02H3/06 ,  H03K5/135 ,  H03K21/10 ,  H03K21/38 ,  H03K19/20

Abstract: The present disclosure relates to configuring parameters of a system. In some examples, a timer duration circuit can be configured to output a timer duration signal defining a time duration for a retry signal based on an impedance of a first circuit coupled at a first node. A logic circuit can be configured to control an output of the retry signal to at least one integrator circuit to control a current to a second node based on one of the timer duration signal and a retry timer signal, and a combination thereof. An output circuit can be configured to output a stop retry signal based on a voltage established by a second circuit at the second node based on its impedance and the current. The stop retry signal can indicate a number of retries that have occurred and can be based on the capacitances of the first and second circuits.

公开(公告)号：US11387834B1

公开(公告)日：2022-07-12

申请号：US17319819

申请日：2021-05-13

Applicant: Texas Instruments Incorporated

Inventor： Pranav Kumar ,  Abhrarup Barman Roy ,  Apoorva Bhatia ,  Arpan Sureshbhai Thakkar ,  Jagdish Chand

IPC: H03L7/091 ,  H03L7/18 ,  H03L7/081 ,  H03L7/099 ,  H03L7/089

Abstract: An example apparatus includes: a first flip flop having a first output and a first reset input, a second flip flop having a first data input, a second output, and a second reset input, the second reset input coupled to the first reset input, a logic gate having a first logic input, a second logic input, and a first logic output, the first logic input coupled to the first output and the second logic input coupled to the second output, a delay cell having a delay cell input and a delay cell output, the delay cell input coupled to the first logic output and the delay cell output coupled to the first reset input and the second reset input, and pulse swallowing circuitry having a circuitry input and a circuitry output, the circuitry input coupled to the second output and the circuitry output coupled to the first data input.