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    Fractional frequency clock divider with direct division
    1.
    发明授权
    Fractional frequency clock divider with direct division 有权

    公开(公告)号：US10153777B2

    公开(公告)日：2018-12-11

    申请号：US15281617

    申请日：2016-09-30

    申请人： Texas Instruments Incorporated

    发明人： Reza Hoshyar ,  Wenting Zhou ,  Ali Kiaei ,  Baher Haroun ,  Ahmad Bahai

    IPC分类号： H03L7/00 ,  H03L7/197 ,  H03L7/16 ,  H03L7/18

    摘要： Disclosed examples include fractional frequency divider circuits, including a counter to provide phase shifted pulse output signals in response to counting of an adjustable integer number NK cycles of an input clock signal, an output circuit to provide an output clock signal having a first edge between first edges of the pulse output signals, as well as a delta-sigma modulator (DSM), clocked by the second pulse output signal to receive a first predetermined value and to provide a DSM output value, and a phase accumulator to receive a step input value representing a sum of the DSM output value and a second predetermined value. The phase accumulator provides a divisor input signal to the counter, and provides a phase adjustment value to the output circuit to control the position of the first edge of the output clock signal between the first edges of the pulse output signals.

    FRACTIONAL FREQUENCY CLOCK DIVIDER WITH DIRECT DIVISION
    3.
    发明申请
    FRACTIONAL FREQUENCY CLOCK DIVIDER WITH DIRECT DIVISION 审中-公开

    公开(公告)号：US20180097523A1

    公开(公告)日：2018-04-05

    申请号：US15281617

    申请日：2016-09-30

    申请人： Texas Instruments Incorporated

    发明人： Reza Hoshyar ,  Wenting Zhou ,  Ali Kiaei ,  Baher Haroun ,  Ahmad Bahai

    IPC分类号： H03L7/197

    CPC分类号： H03L7/1976 ,  H03L7/16 ,  H03L7/18 ,  H03L7/1806 ,  H03L7/197

    摘要： Disclosed examples include fractional frequency divider circuits, including a counter to provide phase shifted pulse output signals in response to counting of an adjustable integer number NK cycles of an input clock signal, an output circuit to provide an output clock signal having a first edge between first edges of the pulse output signals, as well as a delta-sigma modulator (DSM), clocked by the second pulse output signal to receive a first predetermined value and to provide a DSM output value, and a phase accumulator to receive a step input value representing a sum of the DSM output value and a second predetermined value. The phase accumulator provides a divisor input signal to the counter, and provides a phase adjustment value to the output circuit to control the position of the first edge of the output clock signal between the first edges of the pulse output signals.