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公开(公告)号：US12149236B2
公开(公告)日：2024-11-19
申请号：US17827406
申请日：2022-05-27
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Venkatesh Guduri , Ashish Ojha , Priyank Anand , Richeek Maitra
IPC: H03K17/00 , H03K17/30 , H03K17/687
Abstract: In an example, a system includes a first transistor and a second transistor, the first transistor and the second transistor configured to provide current to a load. The system also includes a sense transistor coupled to the first transistor, the sense transistor configured to sense a current flowing through the first transistor. The system includes an amplifier coupled to the sense transistor, where the amplifier includes a first input, a second input, and an output. The system also includes pre-bias circuitry coupled to the amplifier, where the pre-bias circuitry is configured to provide a voltage to the first input of the amplifier responsive to the first transistor being off, where the voltage biases the amplifier.
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公开(公告)号：US20230039198A1
公开(公告)日：2023-02-09
申请号：US17397133
申请日：2021-08-09
Applicant: Texas Instruments Incorporated
Inventor： Ashish Ojha , Krishnamurthy Shankar , Siddhartha Gopal Krishna , Priyank Anand , Ganapathi Hegde
IPC: H03K17/687 , H02P23/00 , H03K5/24
Abstract: A control circuit regulates the propagation delay of a field effect transistor (FET) before the FET transitions to the Miller region by applying a pre-charge current for a fixed duration to the gates of the FET. After the fixed duration, the current is reduced to a lower drive current level which is based on a desired output voltage slew rate. After the FET transitions to the Miller region, the output voltage slews down in accordance with the output voltage slew rate. By regulating the slew-rate of the output voltage in the Miller region and regulating the propagation delay of the FET prior to the Miller region, the control circuit reduces electromagnetic interference (EMI) caused by the switching of the FET, thereby improving electromagnetic compatibility (EMC) of switch mode driver systems without increasing the propagation delay of the FET.
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公开(公告)号：US12179617B2
公开(公告)日：2024-12-31
申请号：US17826822
申请日：2022-05-27
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Priyank Anand , Ashish Ojha , Krishnamurthy Shankar , Venkatesh Guduri
Abstract: Examples of contactor controllers, systems and methods enable quick-turn-off (QTO) using an output voltage of a contactor controller when its supply voltage is below a threshold but does not interfere with QTO when sufficient supply voltage is available. In an example, when VM loss occurs, a high-side (HS) clamp of a contactor controller is disabled, and a low-side (LS) clamp current is generated using the output voltage. The LS clamp current may be adjusted to achieve a desired QTO voltage. In another example, a HS clamp is disabled and the charging of the gate of a LS field-effect transistor (FET) is enabled only when the output voltage increases above a power-off QTO threshold (less than the LS clamp voltage); the QTO voltage is set by a voltage detection and comparison circuit of the contactor controller.
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公开(公告)号：US20230044791A1
公开(公告)日：2023-02-09
申请号：US17397156
申请日：2021-08-09
Applicant: Texas Instruments Incorporated
Inventor： Ashish Ojha , Krishnamurthy Shankar , Siddhartha Gopal Krishna , Priyank Anand , Ganapathi Hegde
Abstract: An apparatus for regulating a slew time of an output voltage of a motor driver system includes a gate current control circuit which has a first input coupled to receive a target slew time and a second input coupled to receive a slew time. The gate current control circuit provides an incremented gate current if the slew time is greater than the target slew time and provides a decremented gate current if the slew time is less than the target slew time. The apparatus includes a gate driver which has a first input coupled to receive a PWM signal and a second input coupled to receive the gate current. The gate driver provides a gate drive signal.
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公开(公告)号：US12113521B2
公开(公告)日：2024-10-08
申请号：US17397133
申请日：2021-08-09
Applicant: Texas Instruments Incorporated
Inventor： Ashish Ojha , Krishnamurthy Shankar , Siddhartha Gopal Krishna , Priyank Anand , Ganapathi Hegde
IPC: H03K17/687 , H02P23/00 , H03K5/24
CPC classification number: H03K17/687 , H02P23/00 , H03K5/24
Abstract: A control circuit regulates the propagation delay of a field effect transistor (FET) before the FET transitions to the Miller region by applying a pre-charge current for a fixed duration to the gates of the FET. After the fixed duration, the current is reduced to a lower drive current level which is based on a desired output voltage slew rate. After the FET transitions to the Miller region, the output voltage slews down in accordance with the output voltage slew rate. By regulating the slew-rate of the output voltage in the Miller region and regulating the propagation delay of the FET prior to the Miller region, the control circuit reduces electromagnetic interference (EMI) caused by the switching of the FET, thereby improving electromagnetic compatibility (EMC) of switch mode driver systems without increasing the propagation delay of the FET.
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Patent Agency Ranking
公开(公告)号：US11469586B2
公开(公告)日：2022-10-11
申请号：US16862674
申请日：2020-04-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Ashish Ojha , Krishnamurthy Shankar , Divyasree J , Siddhartha Gopal Krishna , Sarangan Thirumavalavan
Abstract: A circuit includes a first transistor, a second transistor, and a sense transistor. The first current terminals of the first and second transistors are coupled together at a power supply node. The control terminals of the second and third transistors are coupled together. The second current terminals of the first, second, and third transistors are coupled together. The sense resistor is coupled between the first current terminals of the first and second transistors and the first current terminal of the third transistor. The first and second transistors are configured such that during a first mode of operation, current to a load flows through the first and second transistors, and during a second mode of operation, current to a load is discontinued through the first transistor yet flows through the second transistor.
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公开(公告)号：US11108345B1
公开(公告)日：2021-08-31
申请号：US16828757
申请日：2020-03-24
Applicant: Texas Instruments Incorporated
Inventor： Nicholas James Oborny , Ashish Ojha , Priyank Anand , Clark Douglas Kinnaird , Chinmay Jain , Arun Tej Vemuri
Abstract: A control circuit includes a first high-side transistor coupled between a voltage supply terminal and the first terminal of a DC motor and a second high-side transistor coupled between the voltage supply terminal and the second terminal of the DC motor. The control circuit includes a first low-side transistor coupled between a ground terminal and the first terminal of the DC motor and a second low-side transistor coupled between the ground terminal and the second terminal of the DC motor. The control circuit includes a first pull-up resistor coupled between the voltage supply terminal and a gate terminal of the first low-side transistor and a second pull-up resistor coupled between the voltage supply terminal and a gate terminal of the second low-side transistor. The pull-up resistors apply bias currents to turn ON the first and second low-side transistors to provide a conductive path to brake the DC motor.
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公开(公告)号：US11923799B2
公开(公告)日：2024-03-05
申请号：US17397156
申请日：2021-08-09
Applicant: Texas Instruments Incorporated
Inventor： Ashish Ojha , Krishnamurthy Shankar , Siddhartha Gopal Krishna , Priyank Anand , Ganapathi Hegde
CPC classification number: H02P7/29 , H02H9/001 , H03K17/165
Abstract: An apparatus for regulating a slew time of an output voltage of a motor driver system includes a gate current control circuit which has a first input coupled to receive a target slew time and a second input coupled to receive a slew time. The gate current control circuit provides an incremented gate current if the slew time is greater than the target slew time and provides a decremented gate current if the slew time is less than the target slew time. The apparatus includes a gate driver which has a first input coupled to receive a PWM signal and a second input coupled to receive the gate current. The gate driver provides a gate drive signal.
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公开(公告)号：US20230382246A1
公开(公告)日：2023-11-30
申请号：US17826822
申请日：2022-05-27
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Priyank Anand , Ashish Ojha , Krishnamurthy Shankar , Venkatesh Guduri
Abstract: Examples of contactor controllers, systems and methods enable quick-turn-off (QTO) using an output voltage of a contactor controller when its supply voltage is below a threshold but does not interfere with QTO when sufficient supply voltage is available. In an example, when VM loss occurs, a high-side (HS) clamp of a contactor controller is disabled, and a low-side (LS) clamp current is generated using the output voltage. The LS clamp current may be adjusted to achieve a desired QTO voltage. In another example, a HS clamp is disabled and the charging of the gate of a LS field-effect transistor (FET) is enabled only when the output voltage increases above a power-off QTO threshold (less than the LS clamp voltage); the QTO voltage is set by a voltage detection and comparison circuit of the contactor controller.
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公开(公告)号：US11255920B2
公开(公告)日：2022-02-22
申请号：US16785793
申请日：2020-02-10
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Ashish Ojha , Siddhartha Gopal Krishna , Divyasree J , Krishnamurthy Shankar , Venkata Naresh Kotikelapudi
IPC: G01R31/52 , H03K17/687
Abstract: A circuit includes an input terminal, a first transistor, a second transistor, a comparator, a voltage reference circuit, and a control circuit. The first transistor includes a first terminal coupled to the input terminal. The second transistor includes a first terminal coupled to the input terminal. The comparator includes a first terminal coupled to the input terminal. The voltage reference circuit is coupled to a second terminal of the comparator. The control circuit includes an input, a first output, and a second output. The input is coupled to an output of the comparator. The first output is coupled to a second terminal of the first transistor. The second output is coupled to a second terminal of the second transistor.
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