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公开(公告)号：US20240364234A1
公开(公告)日：2024-10-31
申请号：US18308342
申请日：2023-04-27
Applicant: Texas Instruments Incorporated
Inventor： Samir Pandit , Venkata Naresh Kotikelapudi
IPC: H02M7/5387 , H02M1/088
CPC classification number: H02M7/53871 , H02M1/088
Abstract: In described examples, an integrated circuit includes first and second transistors, a switch, a capacitor, a resistor, and first and second comparators. A first terminal of the switch is coupled to a first terminal of the resistor. A second terminal of the switch is coupled to a second terminal of the resistor, a first terminal of the capacitor, and a gate of the first transistor. The first comparator is configured to receive at the first input a first reference voltage, and an output of the first comparator is coupled to a gate of the second transistor. The second comparator is configured to receive at the first input a second reference voltage. A second input of the second comparator is coupled to a second input of the first comparator. An output of the second comparator is coupled to a control input of the switch.
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公开(公告)号：US20210099115A1
公开(公告)日：2021-04-01
申请号：US16703132
申请日：2019-12-04
Applicant: Texas Instruments Incorporated
IPC: H02P8/12 , H03K17/687
Abstract: An integrated circuit includes an H-bridge circuit having a first output node for coupling to a high-side terminal of an inductor and a second output node for coupling to a low-side terminal of the inductor. A current source is coupled in series with a current sense FET between a digital upper supply voltage and the first output node, wherein during a fast decay mode, a gate of the current sense FET is coupled to be turned on. A current-sense comparator includes a first input coupled to a sensing node between the current source and the current sense FET, a second input coupled to the lower supply voltage and an output coupled to a driver control circuit.
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公开(公告)号：US11777425B2
公开(公告)日：2023-10-03
申请号：US17676610
申请日：2022-02-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Venkata Naresh Kotikelapudi , Laxman Sreekumar , Anand Yadav
Abstract: In accordance with at least one example of the description, a circuit is adapted to be coupled to a coil of a motor via an H-bridge circuit. The circuit includes a duty sensor, a subtractor, and a comparator. The duty sensor is coupled to the coil of the motor and is configured to provide raw run duty data responsive to a coil current through the coil. The subtractor is coupled to the duty sensor and is configured to provide a differential duty signal responsive to a stall duty signal and a run duty signal obtained using the raw run duty data. The comparator is coupled to the subtractor and is configured to provide a stall signal indicative of a stall condition for the motor responsive to the differential duty signal and a threshold value.
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公开(公告)号：US20210099116A1
公开(公告)日：2021-04-01
申请号：US16703403
申请日：2019-12-04
Applicant: Texas Instruments Incorporated
IPC: H02P8/12 , G01R19/165 , H03K5/24 , H03K3/3565 , H02P7/03 , H02P8/22 , H03K17/687 , H03M1/00
Abstract: An integrated circuit includes an H-bridge circuit having a first output node for coupling to a high-side terminal of an inductor and a second output node for coupling to a low-side terminal of the inductor. A current sense FET is coupled between a current source and the lower supply voltage to provide a reference current that includes a peak current limit at a sensing node. A current-sense comparator has a first input coupled to the sensing node, a second input coupled to the second output node and an output coupled to send an output signal towards a driver control circuit. A FET linear detection circuit is coupled to receive a gate voltage of an active low-side power FET and has an output coupled to enable the current-sense comparator when the active low-side power FET is operating in a linear region.
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公开(公告)号：US10931216B1
公开(公告)日：2021-02-23
申请号：US16747673
申请日：2020-01-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Krishnamurthy Shankar , Venkata Naresh Kotikelapudi
Abstract: A stepper driver for a motor includes an H-bridge, a sense transistor coupled to the H-bridge, a voltage-to-current (Vtol) converter, and a sine digital-to-analog converter (DAC). The Vtol converter has a Vtol converter input and a Vtol converter output. The Vtol converter output is coupled to the sense transistor. The sine DAC has a sine DAC digital input, a reference input, and a sine DAC output. The sine DAC output is coupled to the Vtol converter input. The sine DAC includes an R-2R network, an offset control circuit coupled to the R-2R network, and a gain control circuit also coupled to the R-2R network.
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Patent Agency Ranking
公开(公告)号：US20240405701A1
公开(公告)日：2024-12-05
申请号：US18204267
申请日：2023-05-31
Applicant: Texas Instruments Incorporated
Inventor： Ganapathi Shankar , Varun Garg , Venkata Naresh Kotikelapudi
IPC: H02P8/38
Abstract: An example apparatus includes: memory including machine-readable instructions; programmable circuitry configured to execute the machine-readable instructions of the memory configured to: determine a first value of power transferred to a stepper motor during a first operation of the stepper motor; determine a second value of power transferred to the stepper motor during a second operation of the stepper motor; determine a load angle of power delivered by the stepper motor during the first operation and second operation of the stepper motor based on the first value, the second value, and a stall power; and compare the load angle to a stall threshold to detect a stall of the stepper motor.
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公开(公告)号：US11936325B2
公开(公告)日：2024-03-19
申请号：US17680577
申请日：2022-02-25
Applicant: Texas Instruments Incorporated
Inventor： Kaushik Alwala , Venkata Naresh Kotikelapudi
CPC classification number: H02P7/0094 , H02P2207/05
Abstract: A motor control system and method for a brushed direct current (BDC) motor using a compensated and corrected ripple count. Motor control circuitry, for example implemented in digital logic such as a microcontroller, receives a coil current signal and a motor voltage signal. Discontinuities in the coil current signal, are counted to generate a ripple count. An observer function derives an angular frequency model estimate using a computational model for the motor applying motor parameters estimated in an initial estimation interval following startup of the motor. A corrected ripple count is generated based on a comparison of a commutation angle of the motor with an angular position based on the angular frequency model estimate. Compensation for cumulative error over the initial estimation interval is derived from a behavioral motor model applying the estimated motor parameters. A motor drive signal is adjusted based on the compensated corrected ripple count.
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8.发明公开公开(公告)号：US20230253899A1
公开(公告)日：2023-08-10
申请号：US17680577
申请日：2022-02-25
Applicant: Texas Instruments Incorporated
Inventor： Kaushik Alwala , Venkata Naresh Kotikelapudi
IPC: H02P7/00
CPC classification number: H02P7/0094 , H02P2207/05
Abstract: A motor control system and method for a brushed direct current (BDC) motor using a compensated and corrected ripple count. Motor control circuitry, for example implemented in digital logic such as a microcontroller, receives a coil current signal and a motor voltage signal. Discontinuities in the coil current signal, are counted to generate a ripple count. An observer function derives an angular frequency model estimate using a computational model for the motor applying motor parameters estimated in an initial estimation interval following startup of the motor. A corrected ripple count is generated based on a comparison of a commutation angle of the motor with an angular position based on the angular frequency model estimate. Compensation for cumulative error over the initial estimation interval is derived from a behavioral motor model applying the estimated motor parameters. A motor drive signal is adjusted based on the compensated corrected ripple count.
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公开(公告)号：US11368112B2
公开(公告)日：2022-06-21
申请号：US16703132
申请日：2019-12-04
Applicant: Texas Instruments Incorporated
IPC: H02P8/12 , G01R19/165 , H03K5/24 , H03M1/00 , H02P7/03 , H02P8/22 , H03K17/687 , H03K3/3565
Abstract: An integrated circuit includes an H-bridge circuit having a first output node for coupling to a high-side terminal of an inductor and a second output node for coupling to a low-side terminal of the inductor. A current source is coupled in series with a current sense FET between a digital upper supply voltage and the first output node, wherein during a fast decay mode, a gate of the current sense FET is coupled to be turned on. A current-sense comparator includes a first input coupled to a sensing node between the current source and the current sense FET, a second input coupled to the lower supply voltage and an output coupled to a driver control circuit.
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公开(公告)号：US20240330549A1
公开(公告)日：2024-10-03
申请号：US18191863
申请日：2023-03-28
Applicant: Texas Instruments Incorporated
Inventor： Danyal Shamsi , Venkata Naresh Kotikelapudi , Venkateswaran Padmanabhan , Guha Lakshmanan , Saksham Sangwan
IPC: G06F30/3308
CPC classification number: G06F30/3308 , G06F2119/02
Abstract: In described examples, a method of testing an integrated circuit design under verification (DUV) includes selecting first and second stimulus-response data to generate a model, and adjusting model training data in response to model accuracy. The first stimulus-response data is selected from stimulus-response data for a known-good design similar to the DUV. The second stimulus-response data is selected from stimulus-response data for the DUV. The model is trained using the first and second stimulus-response data. A first correlation measure verifies model accuracy with respect to trained DUV stimulus-response data. A second correlation measure verifies model accuracy with respect to untrained DUV stimulus-response data. A fraction of trained DUV stimulus-response datasets in the second stimulus-response data is increased if the first correlation measure is greater than a first threshold, and a fraction of untrained DUV stimulus-response datasets is added if the second correlation measure is less than a second threshold.
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