公开(公告)号：US10312912B2

公开(公告)日：2019-06-04

申请号：US15635924

申请日：2017-06-28

Applicant: Texas Instruments Incorporated

Inventor： Christopher Michael Graves

IPC: H03K19/0185 ,  H03K19/00 ,  H03K17/16

Abstract: A gate control circuit for a tristate output buffer operating in a first voltage domain includes a pull-up circuit coupled between an upper rail and a first gate control signal, a pull-down circuit coupled between a lower rail and a second gate control signal, and a gate isolation switch coupled between the first gate control signal and the second gate control signal. The gate isolation switch includes a first PMOS transistor coupled in parallel with a first NMOS transistor. The first NMOS transistor is controlled by a first enable signal and the first PMOS transistor is controlled by a second enable signal.

公开(公告)号：US09479882B2

公开(公告)日：2016-10-25

申请号：US13787185

申请日：2013-03-06

Applicant: Texas Instruments Incorporated

Inventor： Ball Fan ,  Wenpang David Wang ,  Christopher Michael Graves

IPC: H04R5/033 ,  H04R29/00 ,  H04R1/10

CPC classification number: H04R3/007 ,  H04R1/1041 ,  H04R29/00

Abstract: An audio accessory key detection system (40) includes a host circuit (2-3) coupled to communicate via a microphone line (7) with an accessory circuit (3-3) in either a MSFT mode or a digital communication mode. Depletion mode transistors (44-1,2,3) in the accessory circuit are coupled between keys (15-1,2,3) of the accessory circuit, respectively. The depletion mode transistors are allowed to remain conductive for MSFT mode operation. For digital communications mode operation, the host circuit sends a command via the microphone line to a key detector and controller circuit (29A) in the accessory circuit. In response, a voltage is generated to turn the depletion mode transistors off so as to allow digital communications mode operation between the accessory circuit and the host circuit.

Abstract translation: 音频附件密钥检测系统（40）包括主机电路（2-3），其经由麦克风线路（7）与MSFT模式或数字通信模式中的附件电路（3-3）相连接。 附件电路中的耗尽模式晶体管（44-1,2,3）分别耦合在附件电路的键（15-1,2,3）之间。 耗尽型晶体管被允许保持导通，用于MSFT模式操作。 对于数字通信模式操作，主机电路通过麦克风线路发送命令到附件电路中的键检测器和控制器电路（29A）。 作为响应，产生电压以使耗尽型晶体管截止，从而允许附件电路和主机电路之间的数字通信模式操作。

公开(公告)号：US20170019733A1

公开(公告)日：2017-01-19

申请号：US15277579

申请日：2016-09-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ball Fan ,  Wenpang David Wang ,  Christopher Michael Graves

IPC: H04R3/00

CPC classification number: H04R3/007 ,  H04R1/1041 ,  H04R29/00

Abstract: An audio accessory key detection system (40) includes a host circuit (2-3) coupled to communicate via a microphone line (7) with an accessory circuit (3-3) in either a MSFT mode or a digital communication mode. Depletion mode transistors (44-1,2,3) in the accessory circuit are coupled between keys (15-1,2,3) of the accessory circuit, respectively. The depletion mode transistors are allowed to remain conductive for MSFT mode operation. For digital communications mode operation, the host circuit sends a command via the microphone line to a key detector and controller circuit (29A) in the accessory circuit. In response, a voltage is generated to turn the depletion mode transistors off so as to allow digital communications mode operation between the accessory circuit and the host circuit.

Abstract translation: 音频附件密钥检测系统（40）包括主机电路（2-3），其经由麦克风线路（7）与MSFT模式或数字通信模式中的附件电路（3-3）相连接。 附件电路中的耗尽模式晶体管（44-1,2,3）分别耦合在附件电路的键（15-1,2,3）之间。 耗尽型晶体管被允许保持导通，用于MSFT模式操作。 对于数字通信模式操作，主机电路通过麦克风线路发送命令到附件电路中的键检测器和控制器电路（29A）。 作为响应，产生电压以使耗尽型晶体管截止，从而允许附件电路和主机电路之间的数字通信模式操作。

公开(公告)号：US20140254809A1

公开(公告)日：2014-09-11

申请号：US13787185

申请日：2013-03-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ball Fan ,  Wenpang David Wang ,  Christopher Michael Graves

IPC: H04R29/00

CPC classification number: H04R3/007 ,  H04R1/1041 ,  H04R29/00

Abstract: An audio accessory key detection system (40) includes a host circuit (2-3) coupled to communicate via a microphone line (7) with an accessory circuit (3-3) in either a MSFT mode or a digital communication mode. Depletion mode transistors (44-1,2,3) in the accessory circuit are coupled between keys (15-1,2,3) of the accessory circuit, respectively. The depletion mode transistors are allowed to remain conductive for MSFT mode operation. For digital communications mode operation, the host circuit sends a command via the microphone line to a key detector and controller circuit (29A) in the accessory circuit. In response, a voltage is generated to turn the depletion mode transistors off so as to allow digital communications mode operation between the accessory circuit and the host circuit.

Abstract translation: 音频附件密钥检测系统（40）包括主机电路（2-3），其经由麦克风线路（7）与MSFT模式或数字通信模式中的附件电路（3-3）相连接。 附件电路中的耗尽模式晶体管（44-1,2,3）分别耦合在附件电路的键（15-1,2,3）之间。 耗尽型晶体管被允许保持导通，用于MSFT模式操作。 对于数字通信模式操作，主机电路通过麦克风线路发送命令到附件电路中的键检测器和控制器电路（29A）。 作为响应，产生电压以使耗尽型晶体管截止，从而允许附件电路和主机电路之间的数字通信模式操作。

公开(公告)号：US10462564B2

公开(公告)日：2019-10-29

申请号：US15277579

申请日：2016-09-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ball Fan ,  Wenpang David Wang ,  Christopher Michael Graves

IPC: H04R3/00 ,  H04R29/00 ,  H04R1/10

Abstract: An audio accessory key detection system (40) includes a host circuit (2-3) coupled to communicate via a microphone line (7) with an accessory circuit (3-3) in either a MSFT mode or a digital communication mode. Depletion mode transistors (44-1,2,3) in the accessory circuit are coupled between keys (15-1,2,3) of the accessory circuit, respectively. The depletion mode transistors are allowed to remain conductive for MSFT mode operation. For digital communications mode operation, the host circuit sends a command via the microphone line to a key detector and controller circuit (29A) in the accessory circuit. In response, a voltage is generated to turn the depletion mode transistors off so as to allow digital communications mode operation between the accessory circuit and the host circuit.

公开(公告)号：US10110231B1

公开(公告)日：2018-10-23

申请号：US15635980

申请日：2017-06-28

Applicant: Texas Instruments Incorporated

Inventor： Christopher Michael Graves

IPC: H03K19/0185 ,  H03K3/037 ,  H03K3/356 ,  H03K19/003 ,  H03K19/017 ,  G11C5/14

Abstract: A voltage translator translates an input signal to an output signal spanning a wide range of low voltages. An input buffer receives the input signal. A level shifter provides an output control signal. A gate control circuit provides gate control signals. An output buffer provides the output signal. The level shifter includes a pair of cross coupled P-type metal oxide silicon (PMOS) transistors each in series with an N-type metal oxide silicon (NMOS) transistor. A third NMOS transistor is coupled between an upper rail and a drain of one PMOS transistor; the gate of the third NMOS transistor is controlled by a first input control signal. A fourth NMOS transistor is coupled between the upper rail and a drain of the other PMOS transistor; the gate of the fourth NMOS transistor is controlled by a second input control signal.

公开(公告)号：US10027325B1

公开(公告)日：2018-07-17

申请号：US15635844

申请日：2017-06-28

Applicant: Texas Instruments Incorporated

Inventor： Christopher Michael Graves

IPC: H03L5/00 ,  H03K19/0185 ,  H03K17/687

Abstract: A circuit coupled to receive an input voltage that can span a wide voltage supply range and a voltage translator that includes the circuit are disclosed. The circuit includes a first metal oxide silicon (MOS) transistor having a first conductivity type and a first threshold voltage and a second MOS transistor having the first conductivity type and a second threshold voltage that is lower than the first threshold voltage. The first MOS transistor is coupled in parallel with the second MOS transistor between a first rail and a first signal line; the first MOS transistor and the second MOS transistor each receive a first signal on a respective gate.