公开(公告)号：US12002846B2

公开(公告)日：2024-06-04

申请号：US17500096

申请日：2021-10-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Poornika Fernandes ,  David Matthew Curran ,  Stephen Arlon Meisner ,  Bhaskar Srinivasan ,  Guruvayurappan S. Mathur ,  Scott William Jessen ,  Shih Chang Chang ,  Russell Duane Fields ,  Thomas Terrance Lynch

IPC: H01L21/02 ,  H01L49/02

CPC classification number: H01L28/60 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274

Abstract: In some examples, an integrated circuit comprises a substrate; a first metal layer and a second metal layer positioned above the substrate; a first composite dielectric layer located on the first metal layer, wherein the first composite dielectric layer comprises a first anti-reflective coating; a second composite dielectric layer positioned on the second metal layer, wherein the second composite dielectric layer comprises a second anti-reflective coating; and a capacitor metal layer disposed over the first composite dielectric layer.

公开(公告)号：US11171200B2

公开(公告)日：2021-11-09

申请号：US16584463

申请日：2019-09-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Poornika Fernandes ,  David Matthew Curran ,  Stephen Arion Meisner ,  Bhaskar Srinivasan ,  Guruvayurappan S. Mathur ,  Scott William Jessen ,  Shih Chang Chang ,  Russell Duane Fields ,  Thomas Terrance Lynch

IPC: H01L49/02 ,  H01L21/02

Abstract: In some examples, an integrated circuit comprises a substrate; a first metal layer and a second metal layer positioned above the substrate; a first composite dielectric layer located on the first metal layer, wherein the first composite dielectric layer comprises a first anti-reflective coating; a second composite dielectric layer positioned on the second metal layer, wherein the second composite dielectric layer comprises a second anti-reflective coating; and a capacitor metal layer disposed over the first composite dielectric layer.

公开(公告)号：US10902576B2

公开(公告)日：2021-01-26

申请号：US15497925

申请日：2017-04-26

Applicant: Texas Instruments Incorporated

Inventor： Eric Robert Trumbauer ,  Brant William Paquette ,  Vince Christian Samek ,  Michael Jay Jenson ,  David Matthew Curran ,  Jon Evan Button ,  Charles David Gordon

IPC: G06K9/00 ,  G06T7/00 ,  G06T7/70

Abstract: A method of providing a semiconductor device and a computer-readable medium having instructions for performing the method are disclosed. The method includes receiving a first wafer defect map that defines comparison regions and identifies visual defect locations for a wafer. A format of the comparison regions is determined, with the format chosen from a group including die-to-die, partial-shot-to-partial-shot and full-shot-to-full-shot. If the comparison format is not die-to-die, mapping information is received that provides die locations within the comparison regions. A wafer layout map is provided that identifies die locations within the wafer.

公开(公告)号：US10665663B1

公开(公告)日：2020-05-26

申请号：US16198527

申请日：2018-11-21

Applicant: Texas Instruments Incorporated

Inventor： Poornika Fernandes ,  Bhaskar Srinivasan ,  Guruvayurappan Mathur ,  Abbas Ali ,  David Matthew Curran ,  Neil L. Gardner

IPC: H01L29/00 ,  H01L49/02 ,  H01L27/06 ,  H01L21/02 ,  H01L21/762 ,  H01L21/285 ,  H01L21/3213

Abstract: An integrated circuit (IC) includes a semiconductor surface layer on a substrate including functional circuitry having circuit elements configured together with a metal-to-polysilicon capacitor on the semiconductor surface layer for realizing at least one circuit function. The metal-to-polysilicon capacitor includes a bottom plate including polysilicon, a capacitor dielectric including at least one capacitor dielectric layer on the bottom plate, a top plate on the capacitor dielectric, and contacts through a pre-metal dielectric layer that contact the top plate and contact the bottom plate. In lateral regions relative to the capacitor the capacitor dielectric layer has a thickness in a range between about 5% and about 50% of a thickness of the capacitor dielectric of the metal-to-polysilicon capacitor.

公开(公告)号：US20180047149A1

公开(公告)日：2018-02-15

申请号：US15497925

申请日：2017-04-26

Applicant: Texas Instruments Incorporated

Inventor： Eric Robert Trumbauer ,  Brant William Paquette ,  Vince Christian Samek ,  Michael Jay Jenson ,  David Matthew Curran ,  Jon Evan Button ,  Charles David Gordon

IPC: G06T7/00 ,  G06T7/70

CPC classification number: G06T7/0004 ,  G06T7/001 ,  G06T7/70 ,  G06T2207/30148

Abstract: A method of providing a semiconductor device and a computer-readable medium having instructions for performing the method are disclosed. The method includes receiving a first wafer defect map that defines comparison regions and identifies visual defect locations for a wafer. A format of the comparison regions is determined, with the format chosen from a group including die-to-die, partial-shot-to-partial-shot and full-shot-to-full-shot. If the comparison format is not die-to-die, mapping information is received that provides die locations within the comparison regions. A wafer layout map is provided that identifies die locations within the wafer.