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    Analog capacitor on submicron pitch metal level
    2.
    发明授权
    Analog capacitor on submicron pitch metal level 有权

    公开(公告)号：US10177215B1

    公开(公告)日：2019-01-08

    申请号：US15793690

    申请日：2017-10-25

    申请人： Texas Instruments Incorporated

    发明人： Bhaskar Srinivasan ,  Guru Mathur ,  Stephen Arlon Meisner ,  Shih Chang Chang ,  Corinne Ann Gagnet

    IPC分类号： H01L49/02 ,  H01L27/108 ,  H01L29/66 ,  H01L27/06 ,  H01L29/16 ,  H01L21/02 ,  H01L21/768 ,  H01L29/94

    摘要： A microelectronic device includes a capacitor having a lower plate of interconnect metal, a capacitor dielectric layer with a lower silicon dioxide layer, a silicon oxy-nitride layer, and an upper silicon dioxide layer, and an upper plate over the capacitor dielectric layer. The silicon oxy-nitride layer has an average index of refraction of 1.85 to 1.95 at a wavelength of 248 nanometers. To form the microelectronic device, the lower silicon dioxide layer, the silicon oxy-nitride layer, and the upper silicon dioxide layer are formed in sequence over an interconnect metal layer. The upper plate is formed, leaving the lower silicon dioxide layer, the silicon oxy-nitride layer, and at least a portion of the upper silicon dioxide layer over the interconnect metal layer. An interconnect mask is formed of photoresist over the upper plate and the silicon oxy-nitride layer, using the silicon oxy-nitride layer as an anti-reflection layer.

    Capacitor with improved voltage coefficients
    4.
    发明授权
    Capacitor with improved voltage coefficients 有权

    公开(公告)号：US10157915B1

    公开(公告)日：2018-12-18

    申请号：US15793607

    申请日：2017-10-25

    申请人： Texas Instruments Incorporated

    发明人： Bhaskar Srinivasan ,  Shih Chang Chang ,  Poornika Gayathri Fernandes ,  Haowen Bu ,  Guru Mathur

    IPC分类号： H01L27/08 ,  H01L49/02 ,  H01L27/06 ,  H01L27/108 ,  H01L29/66 ,  H01L21/02 ,  H01L21/82

    摘要： A microelectronic device includes a capacitor having a lower plate of interconnect metal, a capacitor dielectric layer with a lower silicon dioxide layer, a silicon oxy-nitride layer, and an upper silicon dioxide layer, and an upper plate over the upper silicon dioxide layer. The silicon oxy-nitride layer has an average index of refraction of 1.60 to 1.75 at a wavelength of 248 nanometers. To form the microelectronic device, the lower silicon dioxide layer, the silicon oxy-nitride layer, and the upper silicon dioxide layer are formed in sequence over an interconnect metal layer. An upper plate layer is patterned to form the upper plate, leaving the lower silicon dioxide layer and at least half of the silicon oxy-nitride layer over the interconnect metal layer. An interconnect mask is formed of photoresist over the upper plate and the silicon oxy-nitride layer, using the silicon oxy-nitride layer as an anti-reflection layer.

    ANALOG CAPACITOR ON SUBMICRON PITCH METAL LEVEL
    6.
    发明申请
    ANALOG CAPACITOR ON SUBMICRON PITCH METAL LEVEL 审中-公开

    公开(公告)号：US20190157379A1

    公开(公告)日：2019-05-23

    申请号：US16240194

    申请日：2019-01-04

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Bhaskar Srinivasan ,  Guru Mathur ,  Stephen Arlon Meisner ,  Shih Chang Chang ,  Corinne Ann Gagnet

    IPC分类号： H01L49/02 ,  H01L21/768 ,  H01L21/02 ,  H01L27/108 ,  H01L29/16 ,  H01L27/06 ,  H01L29/66

    摘要： An integrated circuit includes a capacitor located over a semiconductor substrate. The capacitor includes a first conductive layer having a first lateral perimeter, and a second conductive layer having a second smaller lateral perimeter. A first dielectric layer is located between the second conductive layer and the first conductive layer. The first dielectric layer has a thinner portion having the first lateral perimeter and a thicker portion having the second lateral perimeter. An interconnect line is located over the substrate, and includes a third conductive layer that is about coplanar with and has about a same thickness as the first conductive layer. A second dielectric layer is located over the third conductive layer. The second dielectric layer is about coplanar with and has about a same thickness as the thinner portion of the first dielectric layer.

    In-situ plasma treatment for thin film resistors
    7.
    发明授权
    In-situ plasma treatment for thin film resistors 有权

    公开(公告)号：US10439020B2

    公开(公告)日：2019-10-08

    申请号：US15855635

    申请日：2017-12-27

    申请人： Texas Instruments Incorporated

    发明人： Abbas Ali ,  Dhishan Kande ,  Qi-Zhong Hong ,  Shih Chang Chang

    IPC分类号： H01L49/02 ,  H01L21/3213 ,  H01L27/01

    摘要： A method of fabricating integrated circuits (ICs) includes depositing a dielectric liner layer on a substrate including a semiconductor surface having a plurality of IC die formed therein each including functional circuitry including a plurality of interconnected transistors. A thin film resistor (TFR) layer including chromium (Cr) is deposited on the dielectric liner layer. The substrate is loaded into a hardmask layer deposition tool that includes a plasma source. The TFR layer is in-situ plasma pre-treated including flowing at least one inert gas and at least one oxidizing gas while in the hardmask layer deposition tool. A hardmask layer is deposited after the plasma pre-treating while remaining in the hardmask layer deposition tool. A pattern is formed on the hardmask layer, and the hardmask layer and TFR layer are etched stopping in the dielectric liner layer to form at least one resistor from the defined TFR layer.