公开(公告)号：US11862117B2

公开(公告)日：2024-01-02

申请号：US17388943

申请日：2021-07-29

Applicant: Texas Instruments Incorporated

Inventor： Stephen Phillip Savage ,  Harsh Dinesh Jhaveri

IPC: G09G5/395 ,  G09G3/34 ,  H03M7/30 ,  G09G5/399

CPC classification number: G09G3/346 ,  G09G5/395 ,  G09G5/399 ,  H03M7/30 ,  G09G2310/08 ,  G09G2340/02 ,  G09G2370/00

Abstract: Method and apparatus for matched buffer decompression. In some examples, a circuit comprising a first data element, a second data element, a first buffer coupled to the first data element, a second buffer coupled to the second data element, compression override logic circuits coupled to the first data element and the second data element, and a parallel register coupled to the compression override logic circuits.

公开(公告)号：US11997430B2

公开(公告)日：2024-05-28

申请号：US17146363

申请日：2021-01-11

Applicant: Texas Instruments Incorporated

Inventor： Noah Alan Robb ,  Harsh Dinesh Jhaveri ,  Priyankar Mathuria

IPC: G02B26/08 ,  B81B7/02 ,  G02B26/10 ,  G11C5/06 ,  G11C11/413 ,  H04N9/31

CPC classification number: H04N9/312 ,  B81B7/02 ,  G02B26/0816 ,  G02B26/0833 ,  G02B26/105 ,  G11C5/063 ,  G11C11/413 ,  H04N9/3152 ,  B81B2201/042 ,  B81B2201/07

Abstract: In a described example, a device includes: a semiconductor substrate; a memory array on the semiconductor substrate, the memory array comprising rows and columns of memory cells in a Manhattan pattern, the memory cells having a pitch in a direction along the columns; and an array of micromirrors in a diamond pattern over the memory cells, the micromirrors coupled to corresponding memory cells, the micromirrors having a diagonal pitch length in the direction along the columns that is between 1.8 times the pitch and 2.2 times the pitch.

公开(公告)号：US20240087539A1

公开(公告)日：2024-03-14

申请号：US18516583

申请日：2023-11-21

Applicant: Texas Instruments Incorporated

Inventor： Stephen Phillip Savage ,  Harsh Dinesh Jhaveri

IPC: G09G3/34 ,  G09G5/395 ,  G09G5/399 ,  H03M7/30

CPC classification number: G09G3/346 ,  G09G5/395 ,  G09G5/399 ,  H03M7/30 ,  G09G2310/08 ,  G09G2340/02 ,  G09G2370/00

Abstract: A circuit includes a first clock having a first clock output and a second clock having a second clock output. The circuit also includes a first buffer having a first buffer input, a second buffer input, and a first buffer output, the second buffer input coupled to the first clock output and a second buffer having a third buffer input, a fourth buffer input, and a second buffer output, the third buffer input coupled to the first buffer output and the fourth buffer input coupled to the second clock output. Additionally, the circuit includes a first element of data memory having a first data input and a first data output, the first data input coupled to the first buffer output and a second element of data memory having a second data input and a second data output, the second data input coupled to the second buffer output.

公开(公告)号：US11705089B2

公开(公告)日：2023-07-18

申请号：US17224399

申请日：2021-04-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Robert Floyd Payne ,  Harsh Dinesh Jhaveri ,  Jeffrey Matthew Kempf

IPC: G09G5/10 ,  G02B27/01 ,  G02B26/08

CPC classification number: G09G5/10 ,  G02B27/0172 ,  G02B2027/014 ,  G09G2320/0646

Abstract: A system includes a spatial light modulator (SLM) configured to project an image. The system also includes a controller coupled to the SLM. The controller is configured to receive the image and determine a brightness level of the image. The controller is also configured to enforce a brightness limit on the image responsive to the brightness level, to produce a reduced image. The controller is configured to instruct a display to display the reduced image.

公开(公告)号：US20220224868A1

公开(公告)日：2022-07-14

申请号：US17146363

申请日：2021-01-11

Applicant: Texas Instruments Incorporated

Inventor： Noah Alan Robb ,  Harsh Dinesh Jhaveri ,  Priyankar Mathuria

IPC: H04N9/31 ,  B81B7/02 ,  G11C11/413 ,  G11C5/06 ,  G02B26/08

Abstract: In a described example, a device includes: a semiconductor substrate; a memory array on the semiconductor substrate, the memory array comprising rows and columns of memory cells in a Manhattan pattern, the memory cells having a pitch in a direction along the columns; and an array of micromirrors in a diamond pattern over the memory cells, the micromirrors coupled to corresponding memory cells, the micromirrors having a diagonal pitch length in the direction along the columns that is between 1.8 times the pitch and 2.2 times the pitch.

公开(公告)号：US20220165223A1

公开(公告)日：2022-05-26

申请号：US17388943

申请日：2021-07-29

Applicant: Texas Instruments Incorporated

Inventor： Stephen Phillip Savage ,  Harsh Dinesh Jhaveri

IPC: G09G3/34 ,  H03M7/30 ,  G09G5/399 ,  G09G5/395

Abstract: Method and apparatus for matched buffer decompression. In some examples, a circuit comprising a first data element, a second data element, a first buffer coupled to the first data element, a second buffer coupled to the second data element, compression override logic circuits coupled to the first data element and the second data element, and a parallel register coupled to the compression override logic circuits.