公开(公告)号：US20220173095A1

公开(公告)日：2022-06-02

申请号：US17675066

申请日：2022-02-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Michael SZELONG ,  James Robert TODD ,  Tobias Bernhard FRITZ ,  Ralf Peter BREDERLOW

IPC: H01L27/08 ,  G01L1/18 ,  H01L49/02

Abstract: An integrated circuit comprises a semiconductor substrate having a surface. A lateral resistor is arranged in a first plane parallel to the surface of the substrate. A vertical reference resistor comprises a layer arranged in a second plane parallel to the surface of the substrate and deeper than the first plane. This layer is doped to promote current flow in the second plane. The vertical reference resistor further comprises a first trench and a second trench coupled between the layer and the surface of the substrate. The first and second trenches are arranged in a vertical direction orthogonal to the first and the second planes and are doped to impede current flow in the vertical direction. A cross-section of the first and second trenches is two-fold rotationally symmetric around the vertical direction, and the lateral resistor and the first and second trenches have the same temperature coefficient.

公开(公告)号：US20200227408A1

公开(公告)日：2020-07-16

申请号：US16428682

申请日：2019-05-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Michael SZELONG ,  James Robert TODD ,  Tobias Bernhard FRITZ ,  Ralf Peter BREDERLOW

IPC: H01L27/08 ,  H01L49/02 ,  G01L1/18

Abstract: An integrated circuit comprises a semiconductor substrate having a surface. A lateral resistor is arranged in a first plane parallel to the surface of the substrate. A vertical reference resistor comprises a layer arranged in a second plane parallel to the surface of the substrate and deeper than the first plane. This layer is doped to promote current flow in the second plane. The vertical reference resistor further comprises a first trench and a second trench coupled between the layer and the surface of the substrate. The first and second trenches are arranged in a vertical direction orthogonal to the first and the second planes and are doped to impede current flow in the vertical direction. A cross-section of the first and second trenches is two-fold rotationally symmetric around the vertical direction, and the lateral resistor and the first and second trenches have the same temperature coefficient.

公开(公告)号：US20180151722A1

公开(公告)日：2018-05-31

申请号：US15865028

申请日：2018-01-08

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann EDWARDS ,  Binghua HU ,  James Robert TODD

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/167 ,  H01L29/10 ,  H01L21/265 ,  H01L29/08 ,  H01L29/06 ,  H01L21/324

CPC classification number: H01L29/7816 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: A laterally diffused metal oxide semiconductor (LDMOS) device includes a substrate having a p-epi layer thereon, a p-body region in the p-epi layer and an ndrift (NDRIFT) region within the p-body to provide a drain extension region. A gate stack includes a gate dielectric layer over a channel region in the p-body region adjacent to and on respective sides of a junction with the NDRIFT region. A patterned gate electrode is on the gate dielectric. A DWELL region is within the p-body region. A source region is within the DWELL region, and a drain region is within the NDRIFT region. An effective channel length (Leff) for the LDMOS device is 75 nm to 150 nm which evidences a DWELL implant that utilized an edge of the gate electrode to delineate an edge of a DWELL ion implant so that the DWELL region is self-aligned to the gate electrode.