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公开(公告)号:US20170125528A1
公开(公告)日:2017-05-04
申请号:US15403748
申请日:2017-01-11
Applicant: Texas Instruments Incorporated
Inventor: Binghua Hu , Sameer P. Pendharkar , Jarvis Benjamin Jacobs
IPC: H01L29/41 , H01L21/324 , H01L21/225 , H01L21/3215 , H01L29/45 , H01L21/02
CPC classification number: H01L29/41 , H01L21/02164 , H01L21/02255 , H01L21/02532 , H01L21/02595 , H01L21/2253 , H01L21/26513 , H01L21/32155 , H01L21/324 , H01L21/743 , H01L21/763 , H01L28/20 , H01L28/40 , H01L29/407 , H01L29/45 , H01L29/945
Abstract: A semiconductor device is formed by forming a deep trench in a substrate and a dielectric liner on sidewalls of the deep trench. A first undoped polysilicon layer is formed on the semiconductor device, extending into the deep trench on the dielectric liner, but not filling the deep trench. Dopants are implanted into the first polysilicon layer. A second layer of polysilicon is formed on the first layer of polysilicon. A thermal drive anneal activates and diffuses the dopants. In one version, the dielectric liner is removed at the bottom of the deep trench before the first polysilicon layer is formed, so that the polysilicon in the deep trench provides a contact to the substrate. In another version, the polysilicon in the deep trench is isolated from the substrate by the dielectric liner.
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公开(公告)号:US09431286B1
公开(公告)日:2016-08-30
申请号:US14555209
申请日:2014-11-26
Applicant: Texas Instruments Incorporated
Inventor: Sameer P Pendharkar , Binghua Hu , Abbas Ali , Henry Litzmann Edwards , John P. Erdeljac , Britton Robbins , Jarvis Benjamin Jacobs
IPC: H01L21/76 , H01L21/761 , H01L29/06 , H01L21/263
CPC classification number: H01L21/761 , H01L21/263 , H01L21/26513 , H01L21/26586 , H01L21/76286 , H01L29/0646
Abstract: A semiconductor device with a buried layer has a deep trench structure abutting the buried layer and a self-aligned sinker along sidewalls of the deep trench structure. The semiconductor device may be formed by forming a portion of a deep trench down to the buried layer, and implanting dopants into a substrate of the semiconductor device along sidewalls of the deep trench, and subsequently forming a remainder of the deep trench extending below the buried layer. Alternatively, the semiconductor device may be formed by forming the deep trench to extend below the buried layer, and subsequently implanting dopants into the substrate of the semiconductor device along sidewalls of the deep trench.
Abstract translation: 具有埋层的半导体器件具有邻近掩埋层的深沟槽结构和沿着深沟槽结构的侧壁的自对准沉降片。 半导体器件可以通过将深沟槽的一部分向下形成到掩埋层上,并且通过深沟槽的侧壁将掺杂剂注入到半导体器件的衬底中,并且随后形成深埋在沟槽下面的其余部分 层。 或者,半导体器件可以通过形成深沟槽以在掩埋层下方延伸而形成,并且随后沿着深沟槽的侧壁将掺杂剂注入到半导体器件的衬底中。
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公开(公告)号:US20240290844A1
公开(公告)日:2024-08-29
申请号:US18652020
申请日:2024-05-01
Applicant: Texas Instruments Incorporated
Inventor: Mahalingam Nandakumar , Alexei Sadovnikov , Henry Litzmann Edwards , Jarvis Benjamin Jacobs
IPC: H01L29/26 , H01L21/8238 , H01L27/092 , H01L29/66 , H01L29/78
CPC classification number: H01L29/26 , H01L21/823892 , H01L27/092 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
Abstract: A semiconductor device including drain extended metal oxide semiconductor field effect transistor (MOSFET) includes a source region and a drain region each having a first dopant type spaced apart along a surface of a semiconductor material having a second opposite conductivity type. A gate electrode over the semiconductor material surface between the source region and the drain region. A diffusion suppression implant region in the semiconductor material extends from the source region under the gate electrode. The diffusion suppression implant region includes a body region having the second opposite conductivity type and comprises at least one of carbon, nitrogen, and fluorine.
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公开(公告)号:US09583579B2
公开(公告)日:2017-02-28
申请号:US15191656
申请日:2016-06-24
Applicant: Texas Instruments Incorporated
Inventor: Binghua Hu , Sameer P. Pendharkar , Jarvis Benjamin Jacobs
IPC: H01L27/108 , H01L29/40
CPC classification number: H01L29/41 , H01L21/02164 , H01L21/02255 , H01L21/02532 , H01L21/02595 , H01L21/2253 , H01L21/26513 , H01L21/32155 , H01L21/324 , H01L21/743 , H01L21/763 , H01L28/20 , H01L28/40 , H01L29/407 , H01L29/45 , H01L29/945
Abstract: A semiconductor device is formed by forming a deep trench in a substrate and a dielectric liner on sidewalls of the deep trench. A first undoped polysilicon layer is formed on the semiconductor device, extending into the deep trench on the dielectric liner, but not filling the deep trench. Dopants are implanted into the first polysilicon layer. A second layer of polysilicon is formed on the first layer of polysilicon. A thermal drive anneal activates and diffuses the dopants. In one version, the dielectric liner is removed at the bottom of the deep trench before the first polysilicon layer is formed, so that the polysilicon in the deep trench provides a contact to the substrate. In another version, the polysilicon in the deep trench is isolated from the substrate by the dielectric liner.
Abstract translation: 半导体器件通过在衬底中形成深沟槽和在深沟槽的侧壁上形成介电衬垫来形成。 第一未掺杂多晶硅层形成在半导体器件上,延伸到电介质衬垫上的深沟槽中,但不填充深沟槽。 将掺杂剂注入到第一多晶硅层中。 在第一多晶硅层上形成第二层多晶硅。 热驱动退火激活并扩散掺杂剂。 在一个版本中,在形成第一多晶硅层之前,在深沟槽的底部去除电介质衬垫,使得深沟槽中的多晶硅提供与衬底的接触。 在另一种形式中,深沟槽中的多晶硅通过电介质衬垫从衬底隔离。
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公开(公告)号:US20140342521A1
公开(公告)日:2014-11-20
申请号:US14451485
申请日:2014-08-05
Applicant: Texas Instruments Incorporated
Inventor: Hiroaki Niimi , Jarvis Benjamin Jacobs , Ajith Varghese
IPC: H01L21/324 , H01L21/265 , H01L29/66
CPC classification number: H01L21/324 , H01L21/265 , H01L21/26513 , H01L21/823412 , H01L21/823462 , H01L29/105 , H01L29/66477
Abstract: A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation.
Abstract translation: 两步热处理方法包括在半导体器件的硅衬底中进行离子注入。 在半导体器件上执行第一热处理程序。 在半导体器件上连续执行第二热处理程序以减少由离子注入产生的损伤。
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公开(公告)号:US20220208973A1
公开(公告)日:2022-06-30
申请号:US17156612
申请日:2021-01-24
Applicant: Texas Instruments Incorporated
Inventor: Mahalingam Nandakumar , Alexei Sadovnikov , Henry Litzmann Edwards , Jarvis Benjamin Jacobs
IPC: H01L29/26 , H01L27/092 , H01L29/66 , H01L29/78 , H01L21/8238
Abstract: A semiconductor device including drain extended metal oxide semiconductor field effect transistor (MOSFET) includes a source region and a drain region each having a first dopant type spaced apart along a surface of a semiconductor material having a second opposite conductivity type. A gate electrode over the semiconductor material surface between the source region and the drain region. A diffusion suppression implant region in the semiconductor material extends from the source region under the gate electrode. The diffusion suppression implant region includes a body region having the second opposite conductivity type and comprises at least one of carbon, nitrogen, and fluorine.
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公开(公告)号:US10566200B2
公开(公告)日:2020-02-18
申请号:US15944550
申请日:2018-04-03
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Abbas Ali , Binghua Hu , Stephanie L. Hilbun , Scott William Jessen , Ronald Chin , Jarvis Benjamin Jacobs
IPC: H01L21/266 , H01L29/66
Abstract: A method to fabricate a transistor comprises: forming a first dielectric layer on a semiconductor substrate; depositing a barrier layer on the first dielectric layer; depositing an anti-reflective coating on the barrier layer; depositing and exposing a pattern in a photoresist layer to radiation followed by etching to provide an opening; etching a portion of the anti-reflective coating below the opening; etching a portion of the barrier layer below the opening to expose a portion of the first dielectric layer; providing an ambient oxidizing agent to grow an oxide region followed by removing the barrier layer; implanting dopants into the semiconductor substrate after removing the barrier layer; removing the first dielectric layer after implanting dopants into the semiconductor substrate; and forming a second dielectric layer after removing the first dielectric layer, wherein the oxide region is grown to be thicker than the second dielectric layer.
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公开(公告)号:US20230154915A1
公开(公告)日:2023-05-18
申请号:US17525167
申请日:2021-11-12
Applicant: Texas Instruments Incorporated
Inventor: Bhaskar Srinivasan , Qi-Zhong Hong , Jarvis Benjamin Jacobs
IPC: H01L27/01 , H01L23/522 , H01L27/13
CPC classification number: H01L27/016 , H01L23/5228 , H01L27/13 , H01L27/1207
Abstract: An electronic device includes a first thin film resistor and a second thin film resistor above a dielectric layer that extends in a first plane of orthogonal first and second directions, the first resistor has three portions with the second portion extending between the first and third portions, and a recess etched into the top side of the second portion by a controlled etch process to increase the sheet resistance of the first resistor for dual thin film resistor integration.
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公开(公告)号:US09865691B2
公开(公告)日:2018-01-09
申请号:US15403748
申请日:2017-01-11
Applicant: Texas Instruments Incorporated
Inventor: Binghua Hu , Sameer P. Pendharkar , Jarvis Benjamin Jacobs
IPC: H01L21/8242 , H01L29/41 , H01L29/45 , H01L21/02 , H01L21/225 , H01L21/3215 , H01L21/324
CPC classification number: H01L29/41 , H01L21/02164 , H01L21/02255 , H01L21/02532 , H01L21/02595 , H01L21/2253 , H01L21/26513 , H01L21/32155 , H01L21/324 , H01L21/743 , H01L21/763 , H01L28/20 , H01L28/40 , H01L29/407 , H01L29/45 , H01L29/945
Abstract: A semiconductor device is formed by forming a deep trench in a substrate and a dielectric liner on sidewalls of the deep trench. A first undoped polysilicon layer is formed on the semiconductor device, extending into the deep trench on the dielectric liner, but not filling the deep trench. Dopants are implanted into the first polysilicon layer. A second layer of polysilicon is formed on the first layer of polysilicon. A thermal drive anneal activates and diffuses the dopants. In one version, the dielectric liner is removed at the bottom of the deep trench before the first polysilicon layer is formed, so that the polysilicon in the deep trench provides a contact to the substrate. In another version, the polysilicon in the deep trench is isolated from the substrate by the dielectric liner.
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公开(公告)号:US09054056B2
公开(公告)日:2015-06-09
申请号:US14451489
申请日:2014-08-05
Applicant: Texas Instruments Incorporated
Inventor: Hiroaki Niimi , Jarvis Benjamin Jacobs , Ajith Varghese
IPC: H01L21/469 , H01L21/324 , H01L21/265 , H01L21/8234 , H01L29/66 , H01L29/10
CPC classification number: H01L21/324 , H01L21/265 , H01L21/26513 , H01L21/823412 , H01L21/823462 , H01L29/105 , H01L29/66477
Abstract: A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation.
Abstract translation: 两步热处理方法包括在半导体器件的硅衬底中进行离子注入。 在半导体器件上执行第一热处理程序。 在半导体器件上连续执行第二热处理程序以减少由离子注入产生的损伤。
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