公开(公告)号：US20240243204A1

公开(公告)日：2024-07-18

申请号：US18522543

申请日：2023-11-29

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Hiroyuki MIYAKE ,  Kei TAKAHASHI ,  Kouhei TOYOTAKA ,  Masashi TSUBUKU ,  Kosei NODA ,  Hideaki KUWABARA

IPC: H01L29/786 ,  G06K19/077 ,  H01L21/8236 ,  H01L23/66 ,  H01L27/088 ,  H01L27/12 ,  H01L29/24 ,  H01L29/26 ,  H01L29/66 ,  G11C7/00 ,  G11C19/28 ,  H02M3/07

CPC classification number: H01L29/78609 ,  G06K19/07758 ,  H01L21/8236 ,  H01L23/66 ,  H01L27/0883 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/26 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696 ,  G11C7/00 ,  G11C19/28 ,  H01L2223/6677 ,  H02M3/07

Abstract: An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor, With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.

公开(公告)号：US12015057B2

公开(公告)日：2024-06-18

申请号：US17156612

申请日：2021-01-24

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Alexei Sadovnikov ,  Henry Litzmann Edwards ,  Jarvis Benjamin Jacobs

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/26 ,  H01L29/66

CPC classification number: H01L29/26 ,  H01L21/823892 ,  H01L27/092 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

Abstract: A semiconductor device including drain extended metal oxide semiconductor field effect transistor (MOSFET) includes a source region and a drain region each having a first dopant type spaced apart along a surface of a semiconductor material having a second opposite conductivity type. A gate electrode over the semiconductor material surface between the source region and the drain region. A diffusion suppression implant region in the semiconductor material extends from the source region under the gate electrode. The diffusion suppression implant region includes a body region having the second opposite conductivity type and comprises at least one of carbon, nitrogen, and fluorine.

公开(公告)号：US11901365B2

公开(公告)日：2024-02-13

申请号：US17308010

申请日：2021-05-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wang-Chun Huang ,  Kai-Chieh Yang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/06 ,  H01L29/26 ,  H01L29/24 ,  H01L29/16 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/10 ,  H01L21/308

CPC classification number: H01L27/1211 ,  H01L21/02527 ,  H01L21/3086 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/1606 ,  H01L29/24 ,  H01L29/26 ,  H01L29/66969 ,  H01L29/785

Abstract: A finFET device that includes a substrate and at least one semiconductor fin extending from the substrate. The fin may include a plurality of wide portions comprising a first semiconductor material and one or more narrow portions. The one or more narrow portions have a second width less than the first width of the wide portions. Each of the one or more narrow portions separates two of the plurality of wide portions from one another such that the plurality of wide portions and the one or more narrow portions are arranged alternatingly in a substantially vertical direction that is substantially perpendicular with a surface of the substrate. The fin may also include a channel layer covering sidewalls of the plurality of wide portions and a sidewall of the one or more narrow portions.

公开(公告)号：US11791218B2

公开(公告)日：2023-10-17

申请号：US16879613

申请日：2020-05-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lung-Kun Chu ,  Mao-Lin Huang ,  Chung-Wei Hsu ,  Jia-Ni Yu ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L21/8238 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78 ,  H01L27/092 ,  H01L29/417 ,  H01L29/66 ,  H01L29/06 ,  H01L29/26 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L21/823821 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/26 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: A method includes providing a structure having a substrate, first and second channel layers over the substrate, and first and second gate dielectric layers over the first and the second channel layers respectively. The method further includes forming a first dipole pattern over the first gate dielectric layer, the first dipole pattern having a first dipole material that is of a first conductivity type; forming a second dipole pattern over the second gate dielectric layer, the second dipole pattern having a second dipole material that is of a second conductivity type opposite to the first conductivity type; and annealing the structure such that elements of the first dipole pattern are driven into the first gate dielectric layer and elements of the second dipole pattern are driven into the second gate dielectric layer.

公开(公告)号：US11777023B2

公开(公告)日：2023-10-03

申请号：US17054515

申请日：2020-10-20

Applicant: Innoscience (Suzhou) Technology Co., Ltd.

Inventor： Weixing Du ,  Jheng-Sheng You

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L29/10 ,  H01L29/26 ,  H01L29/15

CPC classification number: H01L29/7787 ,  H01L29/1075 ,  H01L29/157 ,  H01L29/2003 ,  H01L29/26 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/7788

Abstract: A semiconductor device includes a substrate, a first GaN-based high-electron-mobility transistor (HEMT), a second GaN-based HEMT, a first interconnection, and a second interconnection is provided. The substrate has a plurality of first-type doped semiconductor regions and second-type doped semiconductor regions. The first GaN-based HEMT is disposed over the substrate to cover a first region on the first-type doped semiconductor regions and the second-type doped semiconductor regions in the substrate. The second GaN-based HEMT is disposed over the substrate to cover a second region. The first region is different from the second region. The first interconnection is disposed over and electrically connected to the substrate, forming a first interface. The second interconnection is disposed over and electrically connected to the substrate, forming a second interface. The first interface is separated from the second interface by at least two heterojunctions formed in the substrate.

公开(公告)号：US11742393B2

公开(公告)日：2023-08-29

申请号：US17683749

申请日：2022-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jyh-nan Lin ,  Ding-I Liu ,  Yuh-Ta Fan

IPC: H01L29/26 ,  H01L21/02 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L29/26 ,  H01L21/02172 ,  H01L21/02436 ,  H01L21/7685 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76855 ,  H01L23/53295

Abstract: A semiconductor device includes a metal layer, an insulating layer disposed above the metal layer, and a multi-layer diffusion barrier disposed on the metal layer between the metal layer and the insulating layer. The multi-layer diffusion barrier includes a first material layer including a metallic nitride and a second material layer including a metallic oxide.

公开(公告)号：US20230215935A1

公开(公告)日：2023-07-06

申请号：US18178232

申请日：2023-03-03

Applicant: Taiwan Semiconductor manufacturing Co., Ltd.

Inventor： Tzu-Ching Lin ,  Wei Te Chiang ,  Wei Hao Lu ,  Chii-Horng Li ,  Chien-I Kuo ,  Li-Li Su

IPC: H01L29/66 ,  H01L29/167 ,  H01L29/78 ,  H01L27/088 ,  H01L29/161 ,  H01L21/461 ,  H01L29/08 ,  H01L29/26

CPC classification number: H01L29/66795 ,  H01L29/167 ,  H01L29/7853 ,  H01L27/0886 ,  H01L29/161 ,  H01L21/461 ,  H01L29/0847 ,  H01L29/26 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/0653

Abstract: An embodiment is a method including forming a raised portion of a substrate, forming fins on the raised portion of the substrate, forming an isolation region surrounding the fins, a first portion of the isolation region being on a top surface of the raised portion of the substrate between adjacent fins, forming a gate structure over the fins, and forming source/drain regions on opposing sides of the gate structure, wherein forming the source/drain regions includes epitaxially growing a first epitaxial layer on the fin adjacent the gate structure, etching back the first epitaxial layer, epitaxially growing a second epitaxial layer on the etched first epitaxial layer, and etching back the second epitaxial layer, the etched second epitaxial layer having a non-faceted top surface, the etched first epitaxial layer and the etched second epitaxial layer forming source/drain regions.

公开(公告)号：US20180350625A1

公开(公告)日：2018-12-06

申请号：US16049138

申请日：2018-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yuan-Shun CHAO ,  Chih-Wei KUO

IPC: H01L21/44 ,  H01L29/78 ,  H01L21/285 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/26

CPC classification number: H01L21/44 ,  H01L21/28518 ,  H01L29/0847 ,  H01L29/26 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/66969 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858

Abstract: A semiconductor device includes an isolation insulating layer disposed over a substrate, a fin structure disposed over the substrate, and extending in a first direction in plan view, an upper portion of the fin structure being exposed from the isolation insulating layer, a gate structure disposed over a part of the fin structure, the gate structure extending in a second direction crossing the first direction, and a source/drain structure formed on the upper portion of the fin structure, which is not covered by the gate structure and exposed from the isolation insulating layer. The source/drain structure includes a SiP layer, and an upper portion of the source/drain structure includes an alloy layer of Si, Ge and Ti.

公开(公告)号：US20180269114A1

公开(公告)日：2018-09-20

申请号：US15982070

申请日：2018-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Tsun LIU

IPC: H01L21/8238 ,  H01L29/78 ,  H01L21/311 ,  H01L29/66 ,  H01L29/423 ,  H01L29/26 ,  H01L29/165 ,  H01L29/161 ,  H01L29/08 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8258 ,  H01L21/465 ,  H01L21/441

CPC classification number: H01L21/823864 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/441 ,  H01L21/465 ,  H01L21/823814 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/26 ,  H01L29/4232 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on the sidewall of the gate stack structure, and the gate spacers include a top portion and a bottom portion adjoined to the top portion, and the bottom portion slopes to a top surface of the substrate. The semiconductor device structure further includes an epitaxial structure formed adjacent to the gate spacers, and the epitaxial structure is formed below the gate spacers.

公开(公告)号：US10079309B2

公开(公告)日：2018-09-18

申请号：US15178949

申请日：2016-06-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Motoki Nakashima ,  Tatsuya Honda

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/26 ,  H01L29/04 ,  C01G19/00

CPC classification number: H01L29/7869 ,  C01G19/006 ,  C01P2002/72 ,  H01L29/04 ,  H01L29/045 ,  H01L29/26 ,  H01L29/78696

Abstract: An object is to provide a material suitably used for a semiconductor included in a transistor, a diode, or the like. Another object is to provide a semiconductor device including a transistor in which the condition of an electron state at an interface between an oxide semiconductor film and a gate insulating film in contact with the oxide semiconductor film is favorable. Further, another object is to manufacture a highly reliable semiconductor device by giving stable electric characteristics to a transistor in which an oxide semiconductor film is used for a channel. A semiconductor device is formed using an oxide material which includes crystal with c-axis alignment, which has a triangular or hexagonal atomic arrangement when seen from the direction of a surface or an interface and rotates around the c-axis.