公开(公告)号：US20230275007A1

公开(公告)日：2023-08-31

申请号：US17683074

申请日：2022-02-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Makoto SHIBUYA ,  Masamitsu Matsuura ,  Kengo Aoya ,  Anindya Poddar

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/49555 ,  H01L23/3107 ,  H01L24/48 ,  H01L24/85 ,  H01L21/565 ,  H01L21/4842 ,  H01L2224/48245 ,  H01L24/32 ,  H01L2224/32245 ,  H01L24/73 ,  H01L2224/73265

Abstract: In some examples, a semiconductor package comprises a semiconductor die including a device side having a circuit; a mold compound covering the semiconductor die and the circuit; a first lead coupled to the circuit, the first lead having a gullwing shape and emerging from the mold compound in a first horizontal plane, the first lead having a distal end coincident with a second horizontal plane lower than a bottom surface of the mold compound; and a second lead coupled to the circuit, the second lead emerging from the mold compound in the first horizontal plane, the second lead having a distal end coincident with a third horizontal plane higher than a topmost surface of the mold compound, the distal end of the second lead vertically coincident with the mold compound.

公开(公告)号：US20220352055A1

公开(公告)日：2022-11-03

申请号：US17246056

申请日：2021-04-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Makoto SHIBUYA ,  Makoto YOSHINO ,  Kengo AOYA

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/49 ,  H01L21/48 ,  H01L21/56

Abstract: In some examples, a semiconductor package includes a semiconductor die having a device side and a non-device side opposing the device side. The device side has a circuit formed therein. The package includes a first conductive member having a first surface coupled to the non-device side of the semiconductor die and a second surface opposing the first surface. The second surface is exposed to a top surface of the semiconductor package. The package includes a second conductive member exposed to an exterior of the semiconductor package and coupled to the device side of the semiconductor die. The package includes a plurality of wirebonded members coupled to the second surface of the first conductive member and exposed to the exterior of the semiconductor package. At least one of the wirebonded members in the plurality of wirebonded members has a gauge of at least 5 mils.

公开(公告)号：US20240258214A1

公开(公告)日：2024-08-01

申请号：US18162144

申请日：2023-01-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Makoto SHIBUYA ,  Kengo AOYA

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49565 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3107 ,  H01L24/48 ,  H01L2224/48175

Abstract: An example electronic device includes a substrate having a die pad and a semiconductor device on the die pad electrically connected to the substrate. The device also includes a mold compound over the semiconductor device to provide a packaged electronic device. The packaged electronic device has respective side edges that extend from a first end to terminate in a second end at a distal surface of the mold compound that is spaced apart from the substrate. At least one side edge of the mold compound has a respective surface that is orthogonal to the distal surface and includes a notch extending inwardly from the respective surface.

公开(公告)号：US20240128246A1

公开(公告)日：2024-04-18

申请号：US17966530

申请日：2022-10-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kwang-Soo KIM ,  Makoto SHIBUYA ,  Johan STRYDOM

IPC: H01L25/16 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H02M3/00

CPC classification number: H01L25/16 ,  H01L21/4853 ,  H01L23/49844 ,  H01L24/48 ,  H02M3/003 ,  H01L23/49822 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48225 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1306 ,  H01L2924/1426 ,  H01L2924/19041 ,  H01L2924/30107

Abstract: One example includes an apparatus that includes an insulating layer and an electrically conductive layer on the insulating layer. The conductive layer includes a plurality of electrically isolated and conductive regions. A first switch is on a first of the conductive regions, and the first switch has a first terminal and a second terminal. A second switch is on a second of the conductive regions, and the second switch has a third terminal and fourth terminal. A passive component has a fifth terminal and a sixth terminal. The first and third terminals are coupled to the first conductive region. The fourth and sixth terminals are coupled to the second conductive region. The second and fifth terminals are coupled to a third of the conductive regions.

公开(公告)号：US20250079247A1

公开(公告)日：2025-03-06

申请号：US18459119

申请日：2023-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Makoto SHIBUYA ,  Shoichi IRIGUCHI ,  Hideaki MATSUNAGA

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/495

Abstract: In examples, a semiconductor package comprises a semiconductor die having a device side in which circuitry is formed, and a conductive terminal coupled to the device side of the semiconductor die. The package also comprises a mold compound covering the semiconductor die and at least part of the conductive terminal, where the conductive terminal is exposed to an exterior of the mold compound. The mold compound has top and bottom surfaces and a lateral side extending between the top and bottom surfaces. The lateral side includes a first surface contacting the top surface and extending vertically from the top surface toward the bottom surface. The lateral side also includes a second surface contacting the first surface and extending horizontally away from the semiconductor die. The lateral side also includes a third surface contacting the second surface and extending from the second surface to contact the bottom surface. The third surface has physical marks resulting from a singulation process. The first and second surfaces lack physical marks resulting from the singulation process.

公开(公告)号：US20240379509A1

公开(公告)日：2024-11-14

申请号：US18781062

申请日：2024-07-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Makoto SHIBUYA ,  Makoto YOSHINO ,  Kengo AOYA

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/49

Abstract: In some examples, a semiconductor package includes a semiconductor die having a device side and a non-device side opposing the device side. The device side has a circuit formed therein. The package includes a first conductive member having a first surface coupled to the non-device side of the semiconductor die and a second surface opposing the first surface. The second surface is exposed to a top surface of the semiconductor package. The package includes a second conductive member exposed to an exterior of the semiconductor package and coupled to the device side of the semiconductor die. The package includes a plurality of wirebonded members coupled to the second surface of the first conductive member and exposed to the exterior of the semiconductor package. At least one of the wirebonded members in the plurality of wirebonded members has a gauge of at least 5 mils.

公开(公告)号：US20230095630A1

公开(公告)日：2023-03-30

申请号：US17491394

申请日：2021-09-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Makoto SHIBUYA ,  Masamitsu MATSUURA ,  Kengo AOYA

IPC: H01L23/31 ,  H01L23/528 ,  H01L23/00

Abstract: In examples, a wafer chip scale package (WCSP) comprises a semiconductor die including a device side having circuitry formed therein. The WCSP includes a redistribution layer (RDL) including an insulation layer abutting the device side and a metal trace coupled to the device side and abutting the insulation layer. The WCSP includes a conductive member coupled to the metal trace, the conductive member in a first vertical plane that is positioned no farther than a quarter of a horizontal width of the semiconductor die from a vertical axis extending through a center of the semiconductor die. The WCSP includes a lead coupled to the conductive member and extending horizontally past a second vertical plane defined by a perimeter of the semiconductor die.