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公开(公告)号：US20250004492A1
公开(公告)日：2025-01-02
申请号：US18217388
申请日：2023-06-30
Applicant: Texas Instruments Incorporated
Inventor： Harikrishna Parthasarathy , Khyati Bansal , Venkatesh Kadlimatti , Kunal Karanjkar
Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed corresponding to a voltage regulator. An example circuit includes an output terminal; a first transistor including a current terminal and a control terminal coupled to an output terminal; a second transistor including a control terminal and a current terminal coupled to the control terminal of the first transistor; a third transistor including a first current terminal and a second current terminal, the first current terminal of the third transistor coupled to the output terminal; current mirror circuitry including a terminal coupled to the second current terminal of the third transistor; and inverter circuitry including an input terminal and an output terminal, the input terminal coupled to the terminal of the current mirror and the second current terminal of the third transistor, the output terminal coupled to the control terminal of the second transistor.
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Patent Agency Ranking
公开(公告)号：US20230155553A1
公开(公告)日：2023-05-18
申请号：US18155261
申请日：2023-01-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Nitin Agarwal , Kunal Karanjkar , Venkata Ramanan
CPC classification number: H03F1/0211 , H03F3/45197 , H03M1/66 , H03F2203/45044 , H03F2200/375
Abstract: Enhanced operational amplifier trim circuitry and techniques are presented herein. In one implementation, a circuit includes a reference circuit configured to produce a set of reference voltages, and a digital-to-analog conversion (DAC) circuit. The DAC circuit comprises a plurality of transistor pairs, where each pair among the plurality of transistor pairs is configured to provide portions of adjustment currents for an operational amplifier based at least on the set of reference voltages and sizing among transistors of each pair. The circuit also includes drain switching elements coupled to drain terminals of the transistors of each pair and configured to selectively couple one or more of the portions of the adjustment currents to the operational amplifier in accordance with digital trim codes.
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公开(公告)号：US11916516B2
公开(公告)日：2024-02-27
申请号：US18155261
申请日：2023-01-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Nitin Agarwal , Kunal Karanjkar , Venkata Ramanan
CPC classification number: H03F1/0211 , H03F3/45197 , H03M1/66 , H03F2200/375 , H03F2203/45044
Abstract: Enhanced operational amplifier trim circuitry and techniques are presented herein. In one implementation, a circuit includes a reference circuit configured to produce a set of reference voltages, and a digital-to-analog conversion (DAC) circuit. The DAC circuit comprises a plurality of transistor pairs, where each pair among the plurality of transistor pairs is configured to provide portions of adjustment currents for an operational amplifier based at least on the set of reference voltages and sizing among transistors of each pair. The circuit also includes drain switching elements coupled to drain terminals of the transistors of each pair and configured to selectively couple one or more of the portions of the adjustment currents to the operational amplifier in accordance with digital trim codes.
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公开(公告)号：US20230308055A1
公开(公告)日：2023-09-28
申请号：US17897958
申请日：2022-08-29
Applicant: Texas Instruments Incorporated
Inventor： Kunal Karanjkar , Venkata Ramanan R , Srinivasa BS Chakravarthy , Per Torstein Roine
CPC classification number: H03F1/26 , H03F1/304 , H03F2200/375
Abstract: An example device includes: switch circuitry configured to: connect, in a first state based on a control signal, a first switch input to a first switch output and a second switch input to a second switch output; and connect, in a second state based on the control signal, the first switch input to the second switch output and the second switch input to the first switch output; an operational amplifier configured to: generate, in response to the control signal, a first voltage based on a gain and the connections in the first state; and generate, in response to the control signal, a second voltage based on the gain and the connections in the second state; and an Analog to Digital Converter (ADC) configured to convert the first voltage and the second voltage into a digital value based on a multiplication of the input voltage and the gain.
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公开(公告)号：US11558013B2
公开(公告)日：2023-01-17
申请号：US16701629
申请日：2019-12-03
Applicant: Texas Instruments Incorporated
Inventor： Nitin Agarwal , Kunal Karanjkar , Venkata Ramanan
Abstract: Enhanced operational amplifier trim circuitry and techniques are presented herein. In one implementation, a circuit includes a reference circuit configured to produce a set of reference voltages, and a digital-to-analog conversion (DAC) circuit. The DAC circuit comprises a plurality of transistor pairs, where each pair among the plurality of transistor pairs is configured to provide portions of adjustment currents for an operational amplifier based at least on the set of reference voltages and sizing among transistors of each pair. The circuit also includes drain switching elements coupled to drain terminals of the transistors of each pair and configured to selectively couple one or more of the portions of the adjustment currents to the operational amplifier in accordance with digital trim codes.
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公开(公告)号：US20210167731A1
公开(公告)日：2021-06-03
申请号：US16701629
申请日：2019-12-03
Applicant: Texas Instruments Incorporated
Inventor： Nitin Agarwal , Kunal Karanjkar , Venkata Ramanan
Abstract: Enhanced operational amplifier trim circuitry and techniques are presented herein. In one implementation, a circuit includes a reference circuit configured to produce a set of reference voltages, and a digital-to-analog conversion (DAC) circuit. The DAC circuit comprises a plurality of transistor pairs, where each pair among the plurality of transistor pairs is configured to provide portions of adjustment currents for an operational amplifier based at least on the set of reference voltages and sizing among transistors of each pair. The circuit also includes drain switching elements coupled to drain terminals of the transistors of each pair and configured to selectively couple one or more of the portions of the adjustment currents to the operational amplifier in accordance with digital trim codes.
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