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公开(公告)号：US20250080067A1
公开(公告)日：2025-03-06
申请号：US18462083
申请日：2023-09-06
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Debapriya Sahu , Radhika Juluri , Meghna Agrawal
Abstract: Embodiments disclosed herein relate to impedance matching for outputting wide-band signals in radio frequency applications. In an example, a circuit including a low-noise amplifier (LNA) sub-circuit and a tuning sub-circuit is provided. The LNA sub-circuit is configured to couple to an antenna and includes a transistor that includes a gate, a source, and a drain, a first inductor that includes a first terminal configured to couple to the antenna and includes a second terminal, a second inductor that includes a first terminal coupled to the first terminal of the first inductor and includes a second terminal coupled to the gate of the transistor, and a third inductor that includes a first terminal coupled to the source of the transistor and includes a second terminal. The tuning sub-circuit is coupled to the source of the transistor.
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公开(公告)号：US11990916B2
公开(公告)日：2024-05-21
申请号：US17967815
申请日：2022-10-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Meghna Agrawal , Debapriya Sahu
CPC classification number: H03M1/0617 , H03M3/464
Abstract: A circuit includes a digital-to-analog converter (DAC) and a compensation circuit. The DAC has first and second terminals. The compensation circuit includes a capacitor and a transistor. The capacitor has first and second terminals, with the first terminal of the capacitor coupled to the first terminal of the DAC. The transistor has a source coupled to the second terminal of the capacitor, and has a gate coupled to the second terminal of the DAC.
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公开(公告)号：US12096364B2
公开(公告)日：2024-09-17
申请号：US17530059
申请日：2021-11-18
Applicant: Texas Instruments Incorporated
Inventor： Sucheth Suresh Babu Kuncham , Arnab Das , Pranav Sinha , Meghna Agrawal
CPC classification number: H04W52/0229 , H03M1/185 , H04L5/0007 , H04W84/12
Abstract: A Wi-Fi wake-up receiver that receives wake-up signals encoded using orthogonal frequency division multiplexing based on-off keying (OFDM-OOK) modulation includes receiver circuitry having analog envelope detector circuitry configured to non-linearly down-convert an input signal and provide an energy signal for sampling by an analog-to-digital converter (ADC). A wake-up signal for waking up a main radio in a Wi-Fi device can be based on the digitized energy signal. The receiver circuitry can further include, upstream of the envelope detector circuitry and the ADC in the signal chain, an analog mixer for linearly down-converting the input signal and a low-pass filter for attenuating adjacent-channel interferer (ACI) signals prior to the non-linear down-conversion by the envelope detector circuitry. Sampling of the energy signal rather than the higher-bandwidth input signal yield power savings in the ADC and associated circuitry such as a modem.
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公开(公告)号：US11888497B2
公开(公告)日：2024-01-30
申请号：US17893076
申请日：2022-08-22
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Debapriya Sahu , Pranav Sinha , Meghna Agrawal
CPC classification number: H03M1/462 , H03M1/0626 , H03M1/182 , H03M1/468
Abstract: An analog-to-digital converter (ADC) includes a switched capacitor circuit, a comparator, and a control circuit. The switched capacitor circuit has a switch control input and an output, and includes switches coupled to the switch control input and coupled to capacitors. The comparator has an input coupled to the output of the switched capacitor circuit and has an output. The control circuit has a switch control output coupled to the switch control input, has an input coupled to the output of the comparator, and provides switch control signals at the switch control output. Responsive to the switch control signals, the switched capacitor circuit provides an output signal to the comparator that is based on a sample of an analog input signal acquired in a sample acquisition cycle and based on a digital sample value output by the ADC prior to the sample acquisition cycle.
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公开(公告)号：US11476859B1
公开(公告)日：2022-10-18
申请号：US17335667
申请日：2021-06-01
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Meghna Agrawal , Debapriya Sahu
Abstract: A circuit includes a digital-to-analog converter (DAC) and a compensation circuit. The DAC has a first terminal and a second terminal. The compensation circuit has a third terminal and a fourth terminal. The third terminal is coupled to the first terminal, and the fourth terminal is coupled to the second terminal. The compensation circuit is configured to source current into the first terminal responsive to an increase in voltage on the second terminal, and to sink current from the first terminal responsive to a decrease in voltage on the second terminal.
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Patent Agency Ranking
公开(公告)号：US11424756B2
公开(公告)日：2022-08-23
申请号：US17007887
申请日：2020-08-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Debapriya Sahu , Pranav Sinha , Meghna Agrawal
Abstract: A successive approximation register (SAR) analog-to-digital converter includes a capacitive digital-to-analog converter (CDAC), a comparator, and a SAR control circuit. The comparator is coupled to an output of the CDAC. The SAR control circuit is coupled to an input of the CDAC and to an output of the comparator. The SAR control circuit is configured to provide a feedback signal to the CDAC. The CDAC is configured to apply the feedback signal to form an infinite impulse response filter.
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公开(公告)号：US11342890B2
公开(公告)日：2022-05-24
申请号：US16934300
申请日：2020-07-21
Applicant: Texas Instruments Incorporated
Inventor： Meghna Agrawal
Abstract: An apparatus to prevent supply-to-ground current in a comparator is disclosed. The apparatus includes circuitry to determine if first and second output nodes of the comparator have respectively reached first and second logic levels, and circuitry responsive to a determination that the voltage at the first and second output nodes of the comparator has reached the first and second logic levels, to generate a signal. In addition, the apparatus includes circuitry to supply the signal to a transistor, the signal to turn off the transistor and prevent the flow of supply-to-ground current through the comparator.
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公开(公告)号：US10756679B2
公开(公告)日：2020-08-25
申请号：US15858141
申请日：2017-12-29
Applicant: Texas Instruments Incorporated
Inventor： Meghna Agrawal
Abstract: An apparatus to prevent supply-to-ground current in a comparator is disclosed. The apparatus includes circuitry to determine if first and second output nodes of the comparator have respectively reached first and second logic levels, and circuitry responsive to a determination that the voltage at the first and second output nodes of the comparator has reached the first and second logic levels, to generate a signal. In addition, the apparatus includes circuitry to supply the signal to a transistor, the signal to turn off the transistor and prevent the flow of supply-to-ground current through the comparator.
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公开(公告)号：US20240171195A1
公开(公告)日：2024-05-23
申请号：US18425462
申请日：2024-01-29
Applicant: Texas Instruments Incorporated
Inventor： Meghna Agrawal
IPC: H03M3/00
Abstract: A delta-sigma modulator includes a first integrator and a comparator. The comparator's positive input couples to the first integrator's positive output, and the comparator's negative input couples to the first integrator's negative output. A first current DAC comprises a current source device, and first and second transistors. The first transistor has a first transistor control input and first and second current terminals. The first current terminal couples to the current source device, and the second current terminal couples to the first integrator positive output. The second transistor has a second transistor control input and third and fourth current terminals. The third current terminal couples to the current source device, and the fourth current terminal couples to the first integrator negative output. A first capacitive device couples to the second transistor control input and to both the second current terminal and the first integrator positive output.
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公开(公告)号：US11290123B2
公开(公告)日：2022-03-29
申请号：US17183433
申请日：2021-02-24
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Meghna Agrawal
Abstract: A circuit includes a transconductance stage having first and second outputs. The circuit also includes a comparator having first and second inputs. The first input is coupled to the first output, and the second input is coupled to the second output. The comparator includes first through fifth transistors and a pair of cross-coupled transistors. The pair of cross-coupled transistors is coupled to the second current terminals of the first and second transistors. The second current terminal of the third transistor is coupled to the second current terminal of the first transistor, and the first current terminals of the first, second, and third transistors are coupled together. The second current terminals of the fourth and fifth transistors are coupled together and to the control input of the third transistor.
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