FREQUENCY MULTIPLIER CALIBRATION
    1.
    发明公开

    公开(公告)号:US20240223170A1

    公开(公告)日:2024-07-04

    申请号:US18092091

    申请日:2022-12-30

    CPC classification number: H03K5/14 H03K5/00006 H03L7/0807

    Abstract: In some examples, an apparatus includes a delay-based frequency multiplier and an error detection circuit. The delay-based frequency multiplier has a clock input, a multiplier clock output, and a delay calibration input. The error detection circuit has a detection input and a detection output. The detection input is coupled to the multiplier clock output, and the detection output is coupled to the delay calibration input. The error detection circuit is configured to receive a clock signal at the detection input, and provide a period error signal at the detection output based on a time difference between a first edge of the clock signal and a second edge of a delayed version of the clock signal.

    MULTI-PHASE OSCILLATORS
    2.
    发明申请

    公开(公告)号:US20230035350A1

    公开(公告)日:2023-02-02

    申请号:US17389935

    申请日:2021-07-30

    Abstract: An oscillator circuit includes a first BAW oscillator, a first coupling stage, a second BAW oscillator, and a second coupling stage. The first BAW oscillator is configured to generate a first output signal at a frequency. The first coupling stage is coupled to the first BAW oscillator, and is configured to amplify the first output signal. The second BAW oscillator is coupled to the first coupling stage, and is configured to generate a second output signal at the frequency. The second output signal differs in phase from the first output signal. The second coupling stage is coupled to the first BAW oscillator and the second BAW oscillator, and is configured to amplify the second output signal and drive the first BAW oscillator.

    DIGITAL-TO-TIME CONVERTER CALIBRATION
    3.
    发明公开

    公开(公告)号:US20240223201A1

    公开(公告)日:2024-07-04

    申请号:US18193870

    申请日:2023-03-31

    CPC classification number: H03M1/1033 G04F10/005 H03K5/13 H03K2005/00019

    Abstract: In one example, an apparatus includes a MM divider having a clock input, a first divisor input and a MM divider output; a delta-sigma modulator having a second divisor input, a divisor output and a residual output, the divisor output coupled to the first divisor input; a DTC having a clock input, a control input, a calibration input, and an output, the DTC control input coupled to the residual output, and the DTC clock input coupled to the MM divider output; and a calibration circuit having a first calibration control input, a second calibration control input, and a calibration output, the first calibration control input coupled to the DTC output, the second calibration control input coupled to the residual output, and the calibration output coupled to the DTC calibration input.

    BAW OSCILLATORS WITH DUAL BAW TEMPERATURE SENSING

    公开(公告)号:US20230063409A1

    公开(公告)日:2023-03-02

    申请号:US17463406

    申请日:2021-08-31

    Abstract: A temperature compensated oscillator circuit includes a first oscillator, a second oscillator, a first divider, a second divider, a frequency ratio circuit, and a temperature compensation circuit. The first divider is coupled to the first oscillator, and is configured to divide a frequency of a first oscillator signal generated by the first oscillator. The second divider is coupled to the second oscillator, and is configured to divide a frequency of a second oscillator signal generated by the second oscillator. The frequency ratio circuit is coupled to the first divider and the second divider, and is configured to determine a frequency ratio of an output of the first divider to an output of the second divider. The temperature compensation circuit is coupled to the frequency ratio circuit and the first oscillator, and is configured to generate a compensated frequency based on the frequency ratio and the first oscillator signal.

    CALIBRATION OF PARAMETRIC ERROR OF DIGITAL-TO-TIME CONVERTERS

    公开(公告)号:US20220224344A1

    公开(公告)日:2022-07-14

    申请号:US17573323

    申请日:2022-01-11

    Abstract: In some examples, a circuit includes a clock divider and a calibration circuit coupled to the clock divider. The clock divider includes digital-to-time converter (DTC). The calibration circuit configured to determine a gain error and a parametric integrated nonlinearity (INL) error of the DTC, determine a gain adjustment value and a INL adjustment value to compensate for the gain error and the INL error, and modify operation of the DTC according to the gain adjustment value and the INL adjustment value to correct for the gain error and the INL error.

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