公开(公告)号：US20220209782A1

公开(公告)日：2022-06-30

申请号：US17133745

申请日：2020-12-24

Applicant: Texas Instruments Incorporated

Inventor： Narasimhan RAJAGOPAL ,  Chirag Chandrahas SHETTY ,  Neeraj SHRIVASTAVA ,  Prasanth K ,  Eeshan MIGLANI

IPC: H03M1/12 ,  H03L7/081 ,  H03K5/24

Abstract: A method of using an analog-to-digital converter system includes receiving a sampled voltage corresponding to one of an input voltage and a known voltage, causing preamplifiers to generate output signals based on the sampled voltage, generating first and second signals based on the output signals, causing a delay-resolving delay-to-digital backend to generate a single-bit digital signal representing an order of receipt of the first and second signals, and adjusting one or more of the preamplifiers based on the digital signal. The disclosure also relates to a system which includes a voltage-to-delay frontend and a delay-resolving backend, and to a method which includes causing a delay comparator to generate a single-bit digital signal representing an order of receipt of input signals, causing the comparator to transmit a residue delay signal to a succeeding comparator, and transmitting a signal to adjust one or more of the preamplifiers based on the digital signal.

公开(公告)号：US20250023575A1

公开(公告)日：2025-01-16

申请号：US18524652

申请日：2023-11-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rishi SOUNDARARAJAN ,  Visvesvaraya Appala PENTAKOTA ,  Sai Vikas KANDIMALLA ,  Neeraj SHRIVASTAVA ,  Eeshan MIGLANI

IPC: H03M1/10

Abstract: An analog-to-digital converter (ADC) includes: a time-domain ADC core; and a calibration circuit. The time-domain ADC core includes: a first delay-to-digital stage having a terminal; a second delay-to-digital stage having a terminal; a third delay-to-digital stage having a terminal. The calibration circuitry is coupled to the terminal of the first delay-to-digital stage, the terminal of the second delay-to-digital stage, and the terminal of the third delay-to-digital stage of stages. The calibration circuitry is configured to calibrate the first delay-to-digital stage, the second delay-to-digital stage, and the third delay-to-digital stage based on a zero-crossing calibration and an over-range calibration. The over-range calibration sets a maximum threshold and a minimum threshold for the time-domain ADC relative to a reference voltage.

公开(公告)号：US20200169279A1

公开(公告)日：2020-05-28

申请号：US16692006

申请日：2019-11-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sarma Sundareswara GUNTURI ,  Chandrasekhar SRIRAM ,  Jawaharlal TANGUDU ,  Eeshan MIGLANI ,  Jagannathan VENKATARAMAN

IPC: H04B1/30 ,  H04B1/10

Abstract: A non-linearity correction module, an optional droop corrector, and a zero-IF receiver with the non-linearity correction module and an optional droop corrector, wherein the non-linearity correction module is configured to generate a non-linearity term scaled to mitigate an inter-modulation component term of a RF signal received by the zero-IF receiver based on a test signal to enhance linearity in the zero-IF receiver and the optional droop corrector is configured to compensate a droop within a signal band of interest, caused by an analog low pass filter filtering a RF signal received by the zero-IF receiver, before a down-converted RF signal is fed into the non-linearity module.

公开(公告)号：US20220190856A1

公开(公告)日：2022-06-16

申请号：US17689627

申请日：2022-03-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sarma Sundareswara GUNTURI ,  Jagannathan VENKATARAMAN ,  Jawaharlal TANGUDU ,  Narasimhan RAJAGOPAL ,  Eeshan MIGLANI

IPC: H04B1/10 ,  H04B1/40 ,  H03G3/30 ,  H04B1/12

Abstract: Techniques maintaining receiver reliability, including determining a present attenuation level for an attenuator, wherein the attenuation level is set by a gain controller, determining a relative reliability threshold based on the present attenuation level, receiving a radio frequency (RF) signal, determining a voltage level of the received RF signal, comparing the voltage level of the received RF signal to the relative reliability threshold to determine that a reliability condition exists, and overriding, in response to the determination that the reliability condition exists, the present attenuation level set by the gain controller with an override attenuation level based on the present attenuation level.

公开(公告)号：US20210175914A1

公开(公告)日：2021-06-10

申请号：US17112137

申请日：2020-12-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sarma Sundareswara GUNTURI ,  Jagannathan VENKATARAMAN ,  Jawaharlal TANGUDU ,  Narasimhan RAJAGOPAL ,  Eeshan MIGLANI

IPC: H04B1/10 ,  H04B1/40 ,  H04B1/12 ,  H03G3/30

Abstract: Techniques maintaining receiver reliability, including determining a present attenuation level for an attenuator, wherein the attenuation level is set by a gain controller, determining a relative reliability threshold based on the present attenuation level, receiving a radio frequency (RF) signal, determining a voltage level of the received RF signal, comparing the voltage level of the received RF signal to the relative reliability threshold to determine that a reliability condition exists, and overriding, in response to the determination that the reliability condition exists, the present attenuation level set by the gain controller with an override attenuation level based on the present attenuation level.

公开(公告)号：US20200177130A1

公开(公告)日：2020-06-04

申请号：US16274519

申请日：2019-02-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rahul SHARMA ,  Jagannathan VENKATARAMAN ,  Eeshan MIGLANI ,  Sandeep Kesrimal OSWAL

IPC: H03C1/06 ,  H03C1/60 ,  H04B1/04

Abstract: A system includes a Zero IF transmitter having a mixer and a programmable gain stage. The Zero IF transmitter also includes an intermediate stage between the mixer and the programmable gain stage, wherein the intermediate stage is configured to decouple the mixer and the programmable gain stage.

公开(公告)号：US20190097644A1

公开(公告)日：2019-03-28

申请号：US16204349

申请日：2018-11-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jagannathan VENKATARAMAN ,  Eeshan MIGLANI

IPC: H03M1/08

CPC classification number: H03M1/08 ,  H03K17/162 ,  H03K17/165 ,  H03M1/742

Abstract: At least some embodiments are directed to a system that comprises a differential switch network comprising first and second output nodes, first and second transistors coupled to the network, and first and second resistors coupled to the first and second transistors. The DAC also comprises a voltage source coupled to the first resistor and a ground connection coupled to the second resistor. The DAC further includes a capacitor coupled to the first and second transistors and to the second resistor.

公开(公告)号：US20200177168A1

公开(公告)日：2020-06-04

申请号：US16396873

申请日：2019-04-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nagalinga Swamy Basayya AREMALLAPUR ,  Eeshan MIGLANI ,  Visvesvaraya PENTAKOTA ,  Praxal Sunilkumar SHAH

IPC: H03K3/013 ,  H03K21/10 ,  H03K3/037

Abstract: A spur cancellation circuit for use in a mixed signal circuit. A spur cancellation circuit includes a clock generation circuit, a flip-flop bank, and a control circuit. The clock generation circuit is configured to generate a clock signal. The flip-flop bank is coupled to the clock generation circuit, and includes a plurality of flip-flops configured to be clocked by the clock signal. The control circuit is coupled to the clock generation circuit and the flip-flop bank. The control circuit is configured to individually enable one or more of the flip-flops to change state responsive to the clock signal and consume a predetermined amount of power; and to provide a data value to be clocked into the flip-flops.

公开(公告)号：US20180212614A1

公开(公告)日：2018-07-26

申请号：US15927157

申请日：2018-03-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jagannathan VENKATARAMAN ,  Eeshan MIGLANI

IPC: H03M1/08 ,  H03K17/16

CPC classification number: H03M1/08 ,  H03K17/162 ,  H03K17/165 ,  H03M1/742

Abstract: At least some embodiments are directed to a system that comprises a differential switch network comprising first and second output nodes, first and second transistors coupled to the network, and first and second resistors coupled to the first and second transistors. The DAC also comprises a voltage source coupled to the first resistor and a ground connection coupled to the second resistor. The DAC further includes a capacitor coupled to the first and second transistors and to the second resistor.

公开(公告)号：US20160344404A1

公开(公告)日：2016-11-24

申请号：US15160116

申请日：2016-05-20

Applicant: Texas Instruments Incorporated

Inventor： Eeshan MIGLANI ,  Karthikeyan Gunasekaran

IPC: H03M3/00

CPC classification number: H03M3/464 ,  H03M1/0665 ,  H03M1/66 ,  H03M3/424

Abstract: The disclosure provides a delta sigma modulator. The delta sigma modulator includes a summer. The summer generates an error signal in response to an input signal and a feedback signal. A loop filter is coupled to the summer and generates a filtered signal in response to the error signal. A quantizer is coupled to the loop filter and generates a quantized output signal in response to the filtered signal. A digital to analog converter (DAC) is coupled to the summer, and generates the feedback signal in response to a plurality of selection signals. A modified data weighted averaging (DWA) block is coupled between the quantizer and the DAC. The modified DWA block receives a clock signal and generates the plurality of selection signals in response to the quantized output signal and a primary coefficient. The primary coefficient varies with the clock signal.

Abstract translation: 本公开提供了一种Δ-Σ调制器。 ΔΣ调制器包括一个夏天。 夏天响应于输入信号和反馈信号产生误差信号。 环路滤波器耦合到加法器，并响应于误差信号产生滤波信号。 量化器耦合到环路滤波器并且响应于滤波的信号而产生量化的输出信号。 数模转换器（DAC）耦合到加法器，并响应于多个选择信号产生反馈信号。 在量化器和DAC之间耦合经修改的数据加权平均（DWA）块。 修改的DWA块接收时钟信号，并响应于量化的输出信号和一次系数而产生多个选择信号。 主要系数随时钟信号而变化。