公开(公告)号：US10243573B1

公开(公告)日：2019-03-26

申请号：US15959332

申请日：2018-04-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jagdish Chand Goyal ,  Peeyoosh Mirajkar ,  Shankaranarayana Karantha ,  Ashwin Ravisankar ,  Srikanth Manian ,  Srinivas Theertham

IPC: H03L7/16 ,  G06F1/12 ,  H03D3/24 ,  H03L7/18 ,  H03L7/099 ,  H03L7/085

Abstract: Frequency synthesis is based on phase synchronizing PLL output across REFERENCE and VCO clock domains (including outputs for multiple PLLs), based on an input (REF-Domain) SYNC signal (phase timing reference). A frequency synthesizer includes a VCO to generate VCO_clk and a PLL output circuit, such as a channel divider, to generate PLL_OUT based on VCO_clk (in the VCO-Domain). The VCO loop includes a PD to phase compare an input PD_clock based on REF_CLK, and a VCO feedback signal based on divided VCO_clk (NDIV_out). SYNC alignment circuitry generates a SYNC alignment signal based on SYNC, PD_clk, and NDIV_out (REF-Domain), which is used to synchronize the PLL output circuit and PLL_OUT to SYNC. If a reference divider generates PD_clk, the SYNC alignment circuitry generates a reset to SYNC-align the reference divider. If the VCO loop uses fractional divide, the SYNC alignment circuitry resets the fractional modulator to a known sequence.

公开(公告)号：US10439620B2

公开(公告)日：2019-10-08

申请号：US15715151

申请日：2017-09-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Theertham Srinivas ,  Jagdish Chand Goyal ,  Peeyoosh Mirajkar

IPC: H03L7/087 ,  H03L7/197 ,  H03L7/193

Abstract: A dual-PFD circuit with delay feedback generated by a dual-modulus prescaler based on mode control from a feedback delay generation circuit. The PFD circuit can be used with a PLL feedback divider to divide a VCO clock signal VCO_clk and generate FB and FB_DLY signals. The PLL feedback divider includes a dual modulus prescaler to selectively divide the VCO_clk by either M or M+1 (such as 4/5) based on a divide mode control input to generate a prescaled divide signal, and a programmed counter/divider (N counter/1/N divider) to selectively divide the prescaled divide signal to generate the FB signal, and a delay generation circuit to selectively delay the FB signal by a pre-defined delay to generate the FB_DLY signal. The prescaler is responsive to the pre-defined delay from the delay generation circuit to change divide modes. The dual PFD circuit response to the FB and FB_DLY signals in relation to a reference signal to generate a phase comparison signal. the dual-PFD circuit can be used with a charge-pump coupled to the dual PFD circuit, and responsive the phase comparison signal to generate a frequency tuning voltage, for input to a VCO for generating the VCO clock signal. The dual PFD circuit, charge pump and VCO can be used in a PLL frequency synthesizer.

公开(公告)号：US11977407B2

公开(公告)日：2024-05-07

申请号：US17683185

申请日：2022-02-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Apoorva Bhatia ,  Pranav Kumar ,  Abhrarup Barman Roy ,  Peeyoosh Mirajkar ,  Raghavendra Reddy

IPC: G06F1/12 ,  G06F1/08 ,  H03K3/037 ,  H03K19/20

CPC classification number: G06F1/12 ,  G06F1/08 ,  H03K3/037 ,  H03K19/20

Abstract: In an example, a system is adapted to be coupled to a load device having a load clock. The system includes a clock generation device with a pin. The system also includes a capture circuit coupled to the pin and operable to sample a value at the pin. The system includes a D flip-flop having a data input coupled to the capture circuit, a clock input coupled to a clock, and having an output, where the D flip-flop is operable to provide, at the output, a system reference event (SYSREF) signal to align the load clock to the clock, based at least in part on the value at the pin.

公开(公告)号：US20180091157A1

公开(公告)日：2018-03-29

申请号：US15715151

申请日：2017-09-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Theertham Srinivas ,  Jagdish Chand Goyal ,  Peeyoosh Mirajkar

IPC: H03L7/087 ,  H03L7/197

CPC classification number: H03L7/087 ,  H03L7/193 ,  H03L7/1974 ,  H03L7/1976 ,  H03L2207/10

Abstract: A dual-PFD circuit with delay feedback generated by a dual-modulus prescaler based on mode control from a feedback delay generation circuit. The PFD circuit can be used with a PLL feedback divider to divide a VCO clock signal VCO_clk and generate FB and FB_DLY signals. The PLL feedback divider includes a dual modulus prescaler to selectively divide the VCO_clk by either M or M+1 (such as 4/5) based on a divide mode control input to generate a prescaled divide signal, and a programmed counter/divider (N counter/1/N divider) to selectively divide the prescaled divide signal to generate the FB signal, and a delay generation circuit to selectively delay the FB signal by a pre-defined delay to generate the FB_DLY signal. The prescaler is responsive to the pre-defined delay from the delay generation circuit to change divide modes. The dual PFD circuit response to the FB and FB_DLY signals in relation to a reference signal to generate a phase comparison signal. the dual-PFD circuit can be used with a charge-pump coupled to the dual PFD circuit, and responsive the phase comparison signal to generate a frequency tuning voltage, for input to a VCO for generating the VCO clock signal. The dual PFD circuit, charge pump and VCO can be used in a PLL frequency synthesizer.