公开(公告)号：US20170302287A1

公开(公告)日：2017-10-19

申请号：US15485552

申请日：2017-04-12

Applicant: Texas Instruments Incorporated

Inventor： Srinivas Kumar Reddy Naru ,  Visvesvaraya Pentakota Appala ,  Shagun Dusad ,  Neeraj Shrivastava ,  Viswanathan Nagarajan ,  Ani Xavier ,  Rishi Soundararajan ,  Sai Aditya Nurani ,  Roswald Francis

IPC: H03M1/06 ,  H03M1/12

CPC classification number: H03M1/06 ,  H03M1/1038 ,  H03M1/109 ,  H03M1/1205 ,  H03M1/164 ,  H03M1/361

Abstract: The disclosure provides an analog to digital converter (ADC). The ADC includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.

公开(公告)号：US20230138266A1

公开(公告)日：2023-05-04

申请号：US17515041

申请日：2021-10-29

Applicant: Texas Instruments Incorporated

Inventor： Prasanth K ,  Srinivas Kumar Reddy Naru ,  Visvesvaraya Appala Pentakota

IPC: H03M1/10

Abstract: An example apparatus includes: an analog input; a resistor circuit including a first reference output and a second reference output; a first amplifier including a first analog input, a first reference input, and a first amplifier output, the first analog input coupled to the analog input, the first reference input coupled to the first reference output; a second amplifier including a second analog input, a second reference input, and a second amplifier output, the second analog input coupled to the analog input, the second reference input coupled to the second reference output; a first comparator including a first comparator input, the first comparator input coupled to the first amplifier output; and a second comparator including a second comparator input, the second comparator input coupled to the second amplifier output; a first multiplexer including a first multiplexer input and a first residue output, the first multiplexer input coupled to the first amplifier output; and a second multiplexer including a second multiplexer input and a second residue output, the second multiplexer input coupled to the second amplifier output.

公开(公告)号：US10541700B2

公开(公告)日：2020-01-21

申请号：US16249225

申请日：2019-01-16

Applicant: Texas Instruments Incorporated

Inventor： Srinivas Kumar Reddy Naru ,  Narasimhan Rajagopal ,  Shagun Dusad ,  Viswanathan Nagarajan ,  Visvesvaraya Appala Pentakota

IPC: H03M1/06 ,  H03M1/04 ,  H03M1/16

Abstract: In described examples, a stochastic comparator includes a first comparator that compares an input signal and a primary threshold to generate a first signal. A second comparator compares the input signal and the primary threshold to generate a second signal. A decision block generates a control signal in response to the first signal, the second signal and a PRBS (pseudo random binary sequence) signal. A XOR gate generates a detection signal in response the first signal and the second signal.

公开(公告)号：US10530378B1

公开(公告)日：2020-01-07

申请号：US16249927

申请日：2019-01-17

Applicant: Texas Instruments Incorporated

Inventor： Srinivas Kumar Reddy Naru ,  Nagarajan Viswanathan ,  Visvesvaraya Pentakota

IPC: H03M1/06

Abstract: The disclosure provides a circuit. The circuit includes a zone detection block that generates a control signal in response to an input signal. An amplifier generates an amplified signal in response to the input signal and the control signal. An analog to digital converter (ADC) is coupled to the amplifier and samples the amplified signal to generate a digital signal. A digital corrector is coupled to the zone detection block and the ADC, and transforms the digital signal to generate a rectified signal based on the control signal and an error signal. An error estimator is coupled to the zone detection block and receives the rectified signal as a feedback. The error estimator generates the error signal in response to the control signal and the rectified signal.

公开(公告)号：US11881867B2

公开(公告)日：2024-01-23

申请号：US17467561

申请日：2021-09-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Narasimhan Rajagopal ,  Eeshan Miglani ,  Chirag Chandrahas Shetty ,  Neeraj Shrivastava ,  Shagun Dusad ,  Srinivas Kumar Reddy Naru ,  Nithin Gopinath ,  Charls Babu ,  Shivam Srivastava ,  Viswanathan Nagarajan ,  Jagannathan Venkataraman ,  Harshit Moondra ,  Prasanth K ,  Visvesvaraya Appala Pentakota

IPC: H03M1/10

CPC classification number: H03M1/1019

Abstract: In described examples, a circuit includes a calibration engine. The calibration engine generates multiple input codes. A digital to analog converter (DAC) is coupled to the calibration engine, and generates a first calibration signal in response to a first input code of the multiple input codes. An analog to digital converter (ADC) is coupled to the DAC, and generates multiple raw codes responsive to the first calibration signal. A storage circuit is coupled to the ADC and stores a first output code corresponding to the first input code. The first output code is obtained using the multiple raw codes generated by the ADC.

公开(公告)号：US11689210B2

公开(公告)日：2023-06-27

申请号：US17515041

申请日：2021-10-29

Applicant: Texas Instruments Incorporated

Inventor： Prasanth K ,  Srinivas Kumar Reddy Naru ,  Visvesvaraya Appala Pentakota

IPC: H03M1/10

CPC classification number: H03M1/1009

Abstract: An example apparatus includes: an analog input; a resistor circuit including a first reference output and a second reference output; a first amplifier including a first analog input, a first reference input, and a first amplifier output, the first analog input coupled to the analog input, the first reference input coupled to the first reference output; a second amplifier including a second analog input, a second reference input, and a second amplifier output, the second analog input coupled to the analog input, the second reference input coupled to the second reference output; a first comparator including a first comparator input, the first comparator input coupled to the first amplifier output; and a second comparator including a second comparator input, the second comparator input coupled to the second amplifier output; a first multiplexer including a first multiplexer input and a first residue output, the first multiplexer input coupled to the first amplifier output; and a second multiplexer including a second multiplexer input and a second residue output, the second multiplexer input coupled to the second amplifier output.

公开(公告)号：US11496124B1

公开(公告)日：2022-11-08

申请号：US17488724

申请日：2021-09-29

Applicant: Texas Instruments Incorporated

Inventor： Vinam Arora ,  Srinivas Kumar Reddy Naru

IPC: H03K5/01 ,  G06F1/10 ,  H03K3/84

Abstract: A numerically-controlled oscillator (NCO) includes a phase accumulator (PA) which has a first input adapted to receive a phase increment, a second input adapted to receive a clock signal, and a third input adapted to receive a reset signal. The PA provides an instantaneous phase at an output. The NCO includes a dithered splitter which has an input coupled to receive the instantaneous phase. The dithered splitter dithers the instantaneous phase using a pseudo-random binary sequence (PRBS) and provides a dithered course phase and a dithered fine phase. The NCO includes a polynomial approximation unit which has a first input coupled to receive the dithered course phase and a second input coupled to receive the dithered fine phase. The polynomial approximation unit provides a sequence of numbers representing a discrete sinusoidal signal.

公开(公告)号：US10790841B2

公开(公告)日：2020-09-29

申请号：US16221323

申请日：2018-12-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Srinivas Kumar Reddy Naru ,  Anand Jerry George ,  Shagun Dusad ,  Visvesvaraya Appala Pentakota

IPC: H03M1/00 ,  H03M1/06 ,  H03M1/12 ,  H03M1/46 ,  H03M1/10 ,  H03M1/18

Abstract: A system has a digital-to-analog converter; a reference signal coupled to the digital-to-analog converter; a differential amplifier for applying gain, and for generating output signals as a function of sampled input signals, the reference signal, digital codes, and the gain applied by the differential amplifier coupled to the digital-to-analog converter; and a multi-bit successive-approximation register for determining the digital codes in successive stages coupled to the differential amplifier; and the gain applied by the differential amplifier is corrected based on previously determined digital codes.

公开(公告)号：US10103753B1

公开(公告)日：2018-10-16

申请号：US15836039

申请日：2017-12-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Viswanathan Nagarajan ,  Srinivas Kumar Reddy Naru ,  Narasimhan Rajagopal

IPC: H03M1/10 ,  H03M13/39 ,  H03M1/12 ,  H03M13/11

Abstract: A pipeline ADC comprising an ADC segment and a digital backend coupled to the ADC segment. In some examples the ADC is configured to receive an analog signal, generate a first partial digital code representing a first sample of the analog signal, and generate a second partial digital code representing a second sample of the analog signal. In some examples the digital backend is configured to receive the first and second partial digital codes from the ADC segment, generate a combined digital code based at least partially on the first and second partial digital codes, determine a gain error of the ADC segment based at least partially on a first correlation of a PRBS with a difference between the first and second partial digital codes, and apply a first correction to the combined digital code based at least partially on the gain error of the ADC segment.

公开(公告)号：US12206427B2

公开(公告)日：2025-01-21

申请号：US17588493

申请日：2022-01-31

Applicant: Texas Instruments Incorporated

Inventor： Visvesvaraya Appala Pentakota ,  Srinivas Kumar Reddy Naru ,  Chirag Shetty ,  Eeshan Miglani ,  Neeraj Shrivastava ,  Narasimhan Rajagopal ,  Shagun Dusad

IPC: H03M1/10

Abstract: In described examples, a circuit includes a multiplexer. The multiplexer receives an input voltage and a calibration signal. An analog-to-digital converter (ADC) is coupled to the multiplexer and generates an output code in response to the calibration signal. A storage circuit is coupled to the ADC and stores the input code representative of the calibration signal at an address corresponding to the output code. The stored input code includes an index value and a coarse value.