公开(公告)号：US20240187013A1

公开(公告)日：2024-06-06

申请号：US18440113

申请日：2024-02-13

Applicant: Texas Instruments Incorporated

Inventor： Himanshu Varshney ,  Viswanathan Nagarajan ,  Charls Babu ,  Narasimhan Rajagopal ,  Eeshan Miglani ,  Visvesvaraya A. Pentakota

IPC: H03M1/10 ,  H03M1/00 ,  H03M1/12

CPC classification number: H03M1/1009 ,  H03M1/002 ,  H03M1/10 ,  H03M1/12

Abstract: In described examples, an analog to digital converter (ADC), having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.

公开(公告)号：US11962318B2

公开(公告)日：2024-04-16

申请号：US17568972

申请日：2022-01-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Himanshu Varshney ,  Viswanathan Nagarajan ,  Charls Babu ,  Narasimhan Rajagopal ,  Eeshan Miglani ,  Visvesvaraya A Pentakota

IPC: H03M1/06 ,  H03M1/10 ,  H03M1/00 ,  H03M1/12

CPC classification number: H03M1/1009 ,  H03M1/002 ,  H03M1/10 ,  H03M1/12

Abstract: In described examples, an analog to digital converter (ADC), having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.

公开(公告)号：US12074607B2

公开(公告)日：2024-08-27

申请号：US17825864

申请日：2022-05-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Narasimhan Rajagopal ,  Nithin Gopinath ,  Viswanathan Nagarajan ,  Neeraj Shrivastava ,  Visvesvaraya A. Pentakota ,  Harshit Moondra ,  Abhinav Chandra

IPC: H03M1/10

CPC classification number: H03M1/1014

Abstract: A circuit includes a nonlinear analog-to-digital converter (ADC) configured to provide a first digital output based on an analog input signal. The circuit also includes a linearization circuit having a lookup table (LUT) memory configured to store initial calibration data. The linearization circuit is coupled to the nonlinear ADC and is configured to: determine updated calibration data based on the initial calibration data; replace the initial calibration data in the LUT memory with the updated calibration data; and provide a second digital output at a linearization circuit output of the linearization circuit based on the first digital output and the updated calibration data.

公开(公告)号：US11641216B2

公开(公告)日：2023-05-02

申请号：US17689627

申请日：2022-03-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sarma Sundareswara Gunturi ,  Jagannathan Venkataraman ,  Jawaharlal Tangudu ,  Narasimhan Rajagopal ,  Eeshan Miglani

IPC: H04B1/10 ,  H04B1/40 ,  H03G3/30 ,  H04B1/12

Abstract: Techniques maintaining receiver reliability, including determining a present attenuation level for an attenuator, wherein the attenuation level is set by a gain controller, determining a relative reliability threshold based on the present attenuation level, receiving a radio frequency (RF) signal, determining a voltage level of the received RF signal, comparing the voltage level of the received RF signal to the relative reliability threshold to determine that a reliability condition exists, and overriding, in response to the determination that the reliability condition exists, the present attenuation level set by the gain controller with an override attenuation level based on the present attenuation level.

公开(公告)号：US10541700B2

公开(公告)日：2020-01-21

申请号：US16249225

申请日：2019-01-16

Applicant: Texas Instruments Incorporated

Inventor： Srinivas Kumar Reddy Naru ,  Narasimhan Rajagopal ,  Shagun Dusad ,  Viswanathan Nagarajan ,  Visvesvaraya Appala Pentakota

IPC: H03M1/06 ,  H03M1/04 ,  H03M1/16

Abstract: In described examples, a stochastic comparator includes a first comparator that compares an input signal and a primary threshold to generate a first signal. A second comparator compares the input signal and the primary threshold to generate a second signal. A decision block generates a control signal in response to the first signal, the second signal and a PRBS (pseudo random binary sequence) signal. A XOR gate generates a detection signal in response the first signal and the second signal.

公开(公告)号：US11881867B2

公开(公告)日：2024-01-23

申请号：US17467561

申请日：2021-09-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Narasimhan Rajagopal ,  Eeshan Miglani ,  Chirag Chandrahas Shetty ,  Neeraj Shrivastava ,  Shagun Dusad ,  Srinivas Kumar Reddy Naru ,  Nithin Gopinath ,  Charls Babu ,  Shivam Srivastava ,  Viswanathan Nagarajan ,  Jagannathan Venkataraman ,  Harshit Moondra ,  Prasanth K ,  Visvesvaraya Appala Pentakota

IPC: H03M1/10

CPC classification number: H03M1/1019

Abstract: In described examples, a circuit includes a calibration engine. The calibration engine generates multiple input codes. A digital to analog converter (DAC) is coupled to the calibration engine, and generates a first calibration signal in response to a first input code of the multiple input codes. An analog to digital converter (ADC) is coupled to the DAC, and generates multiple raw codes responsive to the first calibration signal. A storage circuit is coupled to the ADC and stores a first output code corresponding to the first input code. The first output code is obtained using the multiple raw codes generated by the ADC.

公开(公告)号：US20220224349A1

公开(公告)日：2022-07-14

申请号：US17568972

申请日：2022-01-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Himanshu Varshney ,  Viswanathan Nagarajan ,  Charls Babu ,  Narasimhan Rajagopal ,  Eeshan Miglani ,  Visvesvaraya A. Pentakota

IPC: H03M1/10

Abstract: In described examples, an analog to digital converter (ADC), having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.

公开(公告)号：US11303312B2

公开(公告)日：2022-04-12

申请号：US17112137

申请日：2020-12-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sarma Sundareswara Gunturi ,  Jagannathan Venkataraman ,  Jawaharlal Tangudu ,  Narasimhan Rajagopal ,  Eeshan Miglani

IPC: H04B1/10 ,  H04B1/40 ,  H03G3/30 ,  H04B1/12

Abstract: Techniques maintaining receiver reliability, including determining a present attenuation level for an attenuator, wherein the attenuation level is set by a gain controller, determining a relative reliability threshold based on the present attenuation level, receiving a radio frequency (RF) signal, determining a voltage level of the received RF signal, comparing the voltage level of the received RF signal to the relative reliability threshold to determine that a reliability condition exists, and overriding, in response to the determination that the reliability condition exists, the present attenuation level set by the gain controller with an override attenuation level based on the present attenuation level.

公开(公告)号：US10103753B1

公开(公告)日：2018-10-16

申请号：US15836039

申请日：2017-12-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Viswanathan Nagarajan ,  Srinivas Kumar Reddy Naru ,  Narasimhan Rajagopal

IPC: H03M1/10 ,  H03M13/39 ,  H03M1/12 ,  H03M13/11

Abstract: A pipeline ADC comprising an ADC segment and a digital backend coupled to the ADC segment. In some examples the ADC is configured to receive an analog signal, generate a first partial digital code representing a first sample of the analog signal, and generate a second partial digital code representing a second sample of the analog signal. In some examples the digital backend is configured to receive the first and second partial digital codes from the ADC segment, generate a combined digital code based at least partially on the first and second partial digital codes, determine a gain error of the ADC segment based at least partially on a first correlation of a PRBS with a difference between the first and second partial digital codes, and apply a first correction to the combined digital code based at least partially on the gain error of the ADC segment.

公开(公告)号：US12206427B2

公开(公告)日：2025-01-21

申请号：US17588493

申请日：2022-01-31

Applicant: Texas Instruments Incorporated

Inventor： Visvesvaraya Appala Pentakota ,  Srinivas Kumar Reddy Naru ,  Chirag Shetty ,  Eeshan Miglani ,  Neeraj Shrivastava ,  Narasimhan Rajagopal ,  Shagun Dusad

IPC: H03M1/10

Abstract: In described examples, a circuit includes a multiplexer. The multiplexer receives an input voltage and a calibration signal. An analog-to-digital converter (ADC) is coupled to the multiplexer and generates an output code in response to the calibration signal. A storage circuit is coupled to the ADC and stores the input code representative of the calibration signal at an address corresponding to the output code. The stored input code includes an index value and a coarse value.